I'm following UG071 pp.29 (enclosed) to program V4 using XCF08P.
But after a high-low-high trigger on PROGRAM_B upon powering on, the FPGA was not configured.
- From the oscilloscope, no activity is observed in the data line (D0) between the platform flash and the FPGA.
- The CCLK can be observed and is ticking at 25MHz after power-on.
- I tried changing the CCLK rate in the settings of Generate Bit File, but the CCLK maintains at 25MHz.
- The *.msc file can be loaded into the Platform Flash, passed Verify, just that it cannot configure the FPGA. If I load the *.bit file into the FPGA directly, it works.
Then I found a reference connection diagram from Xilinx, which is different from UG071 pp29 in the CCLK connection:
(both enclosed, see the connections of the CCLK)
Wondering which one I should follow, and what may be the cause of this problem.
Any comments would help! Thanks.