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rkmichaelswa
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Registered: ‎11-01-2016

Virtex 5 - Bitgen ERROR:PhysDesignRules:2066 - ISERDES routethrough error 'DDLY' pin

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Hello,

 

I'm trying to use an ISERDES component in a Virtex 5 device by instantiating an ISERDES_NODELAY unisim component in the design.  All is well until bitgen flags a DRC (ERROR:PhysDesignRules:2066) error. Examining the ISERDES component with fpga_editor I noticed that a signal is attached to the DDLY pin. This input does not appear on the ISERDES_NODELAY nor ISERDES components in the unisim library although it does show up in the ISERDESE1 component, however that won't work in a Virtex 5.

 

I noted in a previous discussion on this topic that the proposed solution is to ground the DDLY input. I would do that if the pin were available to do so.  Any thoughts or suggestions would be greatly appreciated.

 

Thanks,

Robert

 

BTW: The full error message is:

 

   ERROR:PhysDesignRules:2066 - Component tadpole_eth0/rxd0_idelays[0].RXSERD_M is
   configured for ISERDES. A routethru from the /ILOGIC_X0Y24/DDLY to
   /ILOGIC_X0Y24/O pins, configuring a second input path for the DDLY pin is in
   conflict with ISERDES configuration.

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rkmichaelswa
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Registered: ‎11-01-2016

Hey Deepika,

 

That was it! Many thanks. I read through the Virtex 5 user guide and the libraries guide and saw nothing that explains how the pins on the Unisim model match up with the ISERDES component I see in fpga_editor. It wasn't till I saw your response  that I realized that the DDLY input on the ISDERDES could only come from the output of the IDELAY.  How my design connects the IDELAY output to the D input of the ISERDES in VHDL and ends up connected to the DDLY input after synthesis/map/par process seems like magic. :)

 

Thanks again,

Robert

 

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vuppala
Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2012

Hi @rkmichaelswa

 

Here is an answer record that discuss the same error: https://www.xilinx.com/support/answers/43194.html

 

Thanks,

Vinay

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vemulad
Xilinx Employee
Xilinx Employee
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Registered: ‎09-20-2012

Hi @rkmichaelswa

 

Open technology schematic and check if the port driving the D input of ISERDES is driving any other logic, if yes you need to modify the design to avoid this.

Thanks,
Deepika.
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rkmichaelswa
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Registered: ‎11-01-2016

Hey Deepika,

 

That was it! Many thanks. I read through the Virtex 5 user guide and the libraries guide and saw nothing that explains how the pins on the Unisim model match up with the ISERDES component I see in fpga_editor. It wasn't till I saw your response  that I realized that the DDLY input on the ISDERDES could only come from the output of the IDELAY.  How my design connects the IDELAY output to the D input of the ISERDES in VHDL and ends up connected to the DDLY input after synthesis/map/par process seems like magic. :)

 

Thanks again,

Robert

 

View solution in original post

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