Virtex 5: DFS frequency range too restrictive for clkfx

[drgowans]

I have a Virtex 5 FX200T -1 speed part.

I have a DCM setup to take in a 156 MHz clock on CLKIN, and through the CLKFX output a 93.6 MHz clock. 

This is a multiply of 3, divide by 5.

What do I set DFS_FREQUENCY_MODE to? For low frequency DFS mode, the constraints on the CLKIN are too low.  For the high frequency DFS mode, the constraints on the CLKFX are too high.

I can't use CLKDV, because none of the divide values are appropriate.  I can't imagine having to cascade DCMs for this.

The data sheet says:

DFS Low frequency mode:

CLKIN :   1 - 140 MHz         -- BAD for my input clock of 156 MHz.

CLKFX :  32 - 140 MHz       -- Good for my output clock of ~94 MHz.

DFS high frequency mode:

CLKIN:  25 - 350 MHz        -- Good for my input clock of 156 MHz.

CLKFX: 140 - 350 MHz      -- BAD for my output clock of 94 MHz.

So which one should I use?  Or can I not actually do 3/5 of a 156 MHz clock with a Virtex 5 DCM?

Message Edited by drgowans on 04-08-2009 11:14 AM

[gszakacs]

If you don't need a specific relationship between edges of 156 MHz and 93.6 MHz, you could instead

generate 187.2 MHz in high frequency mode and use a fabric flip-flop to divide by 2.  This still only

uses one DCM, you don't need to waste a BUFG for the single flip-flop on the 187.2 MHz net but

you should add one on the flip-flop's Q output.

HTH,

Gabor

[drgowans]

Thanks, that's helpful.  Any idea if it would cause any jitter issues, or in your experience would it be stable enough?  I am inclined to think it would be fine, but if anyone has experiences with this I'd be curious.

I am also wondering if I couldn't run the DCM in one mode or the other and just hope it works anyway, should I take the chance?

-Daniel

[gszakacs]

The fabric flip-flop should not add as much jitter as the DCM does.  If your 93.6 MHz clock is

sensitive to jitter, you may want to use a PLL instead.