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Visitor sktam
Registered: ‎08-04-2015

Virtex 5 Decoupling

I'm running a power integrity analysis for a PWB that I'm working on that has a XC5VLX155-1FFG1153I.  The board has more than the minimum decoupling as recommended in UG203.  I'm aware that the FPGA package has decoupling caps in it but I can't tell what frequency range it covers.   Are there any impedance plots available for the various power forms?

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Scholar austin
Registered: ‎02-27-2008

Re: Virtex 5 Decoupling



The specifics of the decoupling solution is considered proprietary, but I will share what is needed.


The decoupling recommendations for a board are intended to solve most applications.  There are some designs that will have terrible system jitter, and will probably not work as the solution is intended to reduce the power rail impedance to below 1 to 3 milliohms from DC to ~ 500 MHz.


The resonances of the various LC networks that are impossible to avoid generally have their peak between 10 KHz and 50 KHz.  There are other resonances as well at higher frequencies.


In the attached photo you see the step response to a very large instant current step (note:  do not do this!  If this is your use-class, then contact our FAE's).


There are power-integrity expert FAE's out there to help you with your specific case.  As the response is dependent upon the layout and location of all the components (first order most dominant), and the values of the components (second order) and the parasitics of the components (third order);  the resulting response can be 'broken' due to any of the three.  Poor placement, wrong values, and the wrong type of component may all contribute to an unacceptable power distribution network.


What is your current profile?  Are you alternating between high activity and low activity at 33 KHz?  If so, you may be exciting the worst resonace mode, and your power rail is going crazy as a result.


Also look at wp411 which covers it in more detail,




Austin Lesea
Principal Engineer
Xilinx San Jose
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