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Visitor
Visitor
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Registered: ‎05-21-2009

Virtex-5 High-frequency Clock duty cycle


Let me ask one  topic regarding Virtex-5 PLL's
"allowable input duty cycle"

(1)
As written in ds202 table 74.
If we use clock signal higher than 500MHz as an PLL input :
--> "Allowable Input Duty Cycle is  45/55 %"

The word "45/55 %" means =
    Minimum Clock High-pulse period : 45 %
    Maximum Clock Low-pulse period  : 50 %
It is my understanding correct ?


So, Can I use >500 MHz with 56/44 duty cycle for my PLL input ?
    Minimum Clock High-pulse period : 56 %
    Maximum Clock Low-pulse period  : 44 %


(2) Can i use 56/44 duty cyle clock signal for my ISERDES too ?
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