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Registered: ‎08-17-2009

Virtex-5 LVCMOS output speed

Hi all,


if I understand correctly, Xilinx does not specify any output switching speeds and recommends running an IBIS simulation instead. Now setting up a simulation is not that easy and takes a while, therefore I'd like to know if some people could tell me which speeds they experienced. I'm trying to use LVCMOS18 at 250MHz, and I get only about 600mV of output (on the clock pin which is really switching at 250MHz, the data pins look better).

Is this expected behaviour, or do I have some issue with board design or the like here?


Any hints are highly appreciated!



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4 Replies
Registered: ‎07-21-2009

Hmmm....   A 250MHz 50% duty cycle clock has a 2nS pulse width.  Still, I would think you could do better than 600mV.


Just for sanity check, what's the bandwidth of your scope and probe?  If they aren't at least 1GHz, you might be seeing some attenuation due to your test rig.


How are you driving a 250MHz clock out of the FPGA?  The classic method is to use an ODDR output cell.  Is that what you are using?


Do you have any LVCMOS33-capable output pins available, for comparison to the 250MHz LVCMOS18 output?


P.S. -- next time, consider LVDS (differential) for signals faster than 200MHz.  Do you agree?


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Registered: ‎02-27-2008



In addition to the suggestions you have already received, download a free version os spice, and run some simulations.


Model the IO pin as a perfect pulse voltage source, with rise and fall times of about 300 picoseconds.  Use a 20 to 50 ohm resistor in series with it to model the output impedance.


Then load the "IO pin" with 10pf, 20pf, 50pf, and so on, run it through a transmission line, drive some resistive loads, etc. and see what happens. This will give you a good idea of what is happening.


Likely, you are looking at oscilloscopes without sufficient bandwidth to measure what you wish to measure, poor signal integrity (impedance mismatch, too long a ground lead on the 'scope, etc.).


The IBIS file does provide (in ASCII) important driver information, that can be hand placed into a simple spice simulation, as I have suggested above.  More advanced versions of spice will read the IBIS model, as well (hspice).


Austin Lesea
Principal Engineer
Xilinx San Jose
Registered: ‎08-14-2007

Another sanity check -- Is the pin set to SLEW=FAST?

I think the default slew is SLOW, which definitely won't run 250 MHz.

-- Gabor
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Registered: ‎12-20-2012

I am not quite sure if you can observe this signal using an oscilloscope. There might be impedance matching issues or insufficient driving current issues for LVCMOS pins. If you have any green LCD on your board, there must be a LVCMOS-TTL level shifter for your LCD hence you may use its data pins as TTL outputs. I used them and I got a radar triggering signal (100Khz-duty cycle is %0.5-50ns pulse length) out of these pins


Make sure you use an OBUF primitive(found in unisim-hdl libraries) for a signal going out of chip in your top level design file and SLEW RATE should be set to FAST in your UCF file for that pin.

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