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Visitor
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Registered: ‎07-13-2009

Virtex 5 PCI-Express Endpoint Block Timing Issues

I'm currently working on a Virtex 5 design with the PCI-Express Endpoint block (hard coded), and I've been getting some timing errors that I can't figure out.

 

 The specific constraints that fail are:

 

TS_PCIe_ep_top_i_ep_i_BU2_U0_pcie_ep0_pcie_blk_clocking_i_clkout1_1 = PERIOD TIMEGRP "PCIe_ep_top_i_ep_i_BU2_U0_pcie_ep0_pcie_blk_clocking_i_clkout1_1" TS_clk100_unbuffered / 1.25 HIGH 50%   

 

TS_PCIe_ep_top_i_ep_i_BU2_U0_pcie_ep0_pcie_blk_clocking_i_clkout0_1 = PERIOD TIMEGRP "PCIe_ep_top_i_ep_i_BU2_U0_pcie_ep0_pcie_blk_clocking_i_clkout0_1" TS_clk100_unbuffered / 2.5 HIGH 50%

 

I do have an earlier version of my design where the constraints are met, and I've tried using directed routing in FPGA Editor using some of the routing paths from that design, but haven't had success with that.  I've also tried all PAR effort levels, and I've tried specifically increasing the routing effort of the PCI-E Endpoint block.  No success there either.

 

Any help would be greatly appreciated.  Let me know what other information I can provide to better explain the problem.

 

--Paul

 

 

Any help would be greatly appreciated.  Let me know what other information I can provide to better explain the problem.

 

--Paul

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