03-12-2009 08:31 AM
I'm currently playing around with the system monitor timings. I'm running the ADC in sequencer mode with averaging. In the simulation, I can read and write over the DRP interface regardless of the busy signal, which is in contrast to the System Monitor User Guide (ug192). After a read operation (DWE = 0, DEN = 1) is initiated, the data is available 10 clock cycles after. Is the simulation model correct and i misread the User Guide?
03-12-2009 09:33 AM
You might have mentioned the page number where you read this information in ug192.
I use the V5 system monitor in continuous sequence with averaging, and I completely ignore the BUSY signal; I left it open. It works fine in simulation as well as hardware.
03-12-2009 11:26 PM
It was page 35/36, but i think i found my mistake. I first thought, i need to check the busy signal, if i may write to the sysmon. But actually, I can write whenever I want and the data is latched into the configuration registers only when busy goes low (and reading from a register is no problem at all).
04-29-2011 07:47 AM
I have used the SYSMON to measure voltage of Vccint and current using xilinx tools without any problem. Now I need to access sysmon registers directly using the DRP.
Using parallel IV cable I wrote a program to control the TAP FSM, I successfully got the IDCODE as a test, however when I try to access the SYSMON registers I always get the same value 0x10840000.
According to the documentation (XAPP139 and UG192) the sequence to get data from registers using jtag DRP is:
- Access SYSMON instruction (1111110111) in SHIFT-IR state.
- goto SHIFT-DR and enter a 32 bits instruction to read:
The following is an instruction to read Vccint max (register 21h)