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Visitor flitch@home
Visitor
4,798 Views
Registered: ‎03-09-2010

Virtex 5 configuration time (for CFI FLASH)

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Hi,

 

We are using a V5 FX130T device, that is self booting from external (CFI) FLASH using master parallel mode. Therefore the V5 does the entire boot process itself (big improvement over V4) by generating each address in turn etc.

 

I have selected CCLK in the bitgen.ut file. Not sure if this is used or not, but seems correct. There appears to be no control for frequency of CCLK and I have not attempted to measure it.

 

When we monitor an external pin that floats high during configuration it appears to be active for about 1.5 seconds. Is configuration really taking this long? As it is 16 bit parallel, I would expect it to be much faster.

 

Although we are loading SW from the same FLASH, I would expect the FPGA to configure as soon as it has got the bitstream.

 

So am I doing something wrong or are these times as expected?

 

Any help appreciated.

 

Many thanks

Peter

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Xilinx Employee
Xilinx Employee
5,896 Views
Registered: ‎01-03-2008

Re: Virtex 5 configuration time (for CFI FLASH)

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The XC5VFX130T has configuration size of 50.4Mbits, the nominal startup frequency for CCLK is 2 MHz and your data width is 16 bits.

 

Using this information, 50.4Mbits/2.0 MHz/16 bits, results in a time of 1.575secs which matches what you are seeing.

 

It is possible to increase the CCLK frequency using a bitgen option "-g ConfigRate #" where # is 2, 6, 9, 13, 17, 20, 24, 27, 31, 35, 38, 42, 46, 49, 53, 56, 60.

 

You need to be careful about how you set the ConfigRate to as there is a wide variance and you must not exceed the frequency of the CFI Flash interface.

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4 Replies
Xilinx Employee
Xilinx Employee
5,897 Views
Registered: ‎01-03-2008

Re: Virtex 5 configuration time (for CFI FLASH)

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The XC5VFX130T has configuration size of 50.4Mbits, the nominal startup frequency for CCLK is 2 MHz and your data width is 16 bits.

 

Using this information, 50.4Mbits/2.0 MHz/16 bits, results in a time of 1.575secs which matches what you are seeing.

 

It is possible to increase the CCLK frequency using a bitgen option "-g ConfigRate #" where # is 2, 6, 9, 13, 17, 20, 24, 27, 31, 35, 38, 42, 46, 49, 53, 56, 60.

 

You need to be careful about how you set the ConfigRate to as there is a wide variance and you must not exceed the frequency of the CFI Flash interface.

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Visitor flitch@home
Visitor
4,773 Views
Registered: ‎03-09-2010

Re: Virtex 5 configuration time (for CFI FLASH)

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Fantastic, thanks.

 

Is there a definitive list of bitgen commands for V5 anywhere?

 

Best wishes

Peter

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Explorer
Explorer
4,766 Views
Registered: ‎09-11-2007

Re: Virtex 5 configuration time (for CFI FLASH)

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In the ISE software manuals, open the Command Line Tools User Guide.  In version 11.4, chapter 15 is BitGen.

 

Barry

Xilinx Employee
Xilinx Employee
4,759 Views
Registered: ‎01-03-2008

Re: Virtex 5 configuration time (for CFI FLASH)

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Use the command line "bitgen -h <arch>" where arch is virtex4, virtex,5, spartan3, etc...
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