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Newbie mrl1000
Newbie
15,147 Views
Registered: ‎05-29-2014

Virtex 5 damage concerns if one powers I/O but leaves core voltage off for a long time

Is there any possibiliy of damaging a V5 if one was to power up the chips I/O voltages (3.3V, 2.5V) but leave the core voltage off for long periods of time (hours) before finally powering on the core voltage?

A design that I am working on has two FPGA parts, one a V5, whose voltages are controlled by the second FPGA. It so happens that the default conditions cause the V5 to be powered on its I/O rails, but its core voltage is off. This happened for long periods of time while I was testing code on the second FPGA. 

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9 Replies
Scholar austin
Scholar
15,139 Views
Registered: ‎02-27-2008

Re: Virtex 5 damage concerns if one powers I/O but leaves core voltage off for a long time

m,


No damage.  As long as you stay at, or below, the absolute maximum ratings in the data sheet, there is no samage.


I would caution that no power to the IO baks means their ESD protection is less, as when banks are powered, the ESD protection is at its best.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Newbie drdavros
Newbie
15,116 Views
Registered: ‎05-30-2014

Re: Virtex 5 damage concerns if one powers I/O but leaves core voltage off for a long time

Hello Austin,

 

If I understand correctly from one of your previous posts that the I/O is controlled by the core, so that if the core is "off" then I/O defined as inputs could even possibly become outputs?

 

"The level shifters from the core (at 1v) to the IO (at Vcco), requires that Vccint (core) be applied first.  If it is not, then any IO, may (or may not) drive high, or pull low, for the brief moments between having Vcco, and not having Vccint.

 

If you can not apply Vccint at the same time, or before Vcco&Vccaux, then design so that you do not care if an IO pulls high, or low, briefly."

 

In this case, the "brief moments" would be hours and the design was not engineered to tolerate this. The part has hundreds of connected I/O and many could have been in contention for long periods. The actual board that was being brought up has since stopped working. It drew slightly increasing amounts of power over several months during the checkout/testing until it stopped working.

 

Thanks for your insight and help.

 

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Scholar austin
Scholar
15,111 Views
Registered: ‎02-27-2008

Re: Virtex 5 damage concerns if one powers I/O but leaves core voltage off for a long time

dr,

 

The device is designed such that all IO are held in tristate until POR (power on) is released, and DONBE goes high.

 

So removing Vccint, Vccaux, or Vcco for the configuration bank will force all IO's tristate, and the device will require all supplies to be present, and will require to be configured again.

 

There were some issues with glitching in some families (I do not recal V5 having any of those issues), but that was ONLY whwen the various supplies were coming up, and then only in some sequences.  If you follow the one in the data sheet, there are no glitches on those parts.


Again, I do not believe V5 had any of that power sequencing glitch behavior at all.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor xilinxdave15
Visitor
15,100 Views
Registered: ‎01-21-2011

Re: Virtex 5 damage concerns if one powers I/O but leaves core voltage off for a long time

Hi Austin,

 

So if Vccint is not present, you are saying that the I/Os will all be tri-state.  But it seems like there is a slight possibility that the I/Os will drive high if Vcco is up before Vccint:

 

"The level shifters from the core (at 1v) to the IO (at Vcco), requires that Vccint (core) be applied first.  If it is not, then any IO, may (or may not) drive high, or pull low, for the brief moments between having Vcco, and not having Vccint."

 

The 2.5V went from 779 to 1.0-ohm to ground, and 3.3V 4.5K to 1.1-ohm to ground. 1.0V is still nominal, around 6-7 ohms.  The weird part is that it was gradual, over the course of a few months, which seems to point to the thousands (millions?) of transistors inside of the part slowly breaking down.

 

Can you think of any other issue that would cause this?  We are handling the board with all proper ESD precautions.  What if GTX 1.0V and/or 1.2V were on while Vccint was 0V?  We're throwing darts at this point.

 

Thanks!

 

 

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Scholar austin
Scholar
15,097 Views
Registered: ‎02-27-2008

Re: Virtex 5 damage concerns if one powers I/O but leaves core voltage off for a long time

Without power,


How do you measure ohms?

 

What voltage is the ohmetter using?

 

The only way to make any senswe of this is to measure current (not ohms) and voltage.

 

Cause what?

 

I stand by the datasheet, in that to measure leakage current, that is done with supplies ON, and with the IO configured as tristate, and done with a pico-ammeter (current measurement capable of resolving down to pico-amperes).

 

The IO as shipped is much less than 1 uA leakage to Vcc, or ground (no pullup or pulldown enabled).

 

The V5 from what you have found was that device that had a brief pull up or pull down (random) while supplies ramped.


Once up (or down) before configuration, they are all tristated (unless you have pullups enabled before configuration -- HSWAP_EN pin is asserted).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
Visitor xilinxdave15
Visitor
15,091 Views
Registered: ‎01-21-2011

Re: Virtex 5 damage concerns if one powers I/O but leaves core voltage off for a long time

It's the same series meter we've been using for the past 5 years or so. We are using a Fluke 115 that is calibrated.  I just measured the voltage that it puts out.  In all of the low manual mode settings (< 1M-ohm) it is putting out 2.5V.

 

Unfortunately, we only have the 28V input current to look at.  Our power circuit consists of a 5V secondary that then feeds all of the other DC/DCs.  The 5.0V started to sag, so we know that this 15W brick was completely maxed out.  It was at 3.1V prior to this failure.

 

We used a thermal imager and can see that the 5V brick and the Xilinx are EXTREMELY hot, very quickly.  The other secondaries are all switchers that are > 90% efficient, so not much heat is getting dumped on those.

 

Originally the 28V idle current was about 0.40A, which is expected.  Then over the course of a few months, the idle current (i.e. no FPGA configuration) grew to 0.78A prior to this failure.

 

What you say here is kind of what I expected WRT leakage currents and the data sheet.  However, I just checked, we do have HSWAP_EN set for pull-ups prior to configuration.  Does Vccint play any role in implementing these internal pull-ups

 

Thanks again for your help.  

 

 

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Scholar austin
Scholar
15,082 Views
Registered: ‎02-27-2008

Re: Virtex 5 damage concerns if one powers I/O but leaves core voltage off for a long time

The HSWAP_EN pin is sensed so as to tuern on the weak pullups before configuration, even before the mode pins are registered (how to configure).

 

So, I do not know if it works with Vccint=0, or not.

Perhaps someone else can chime in.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Xilinx Employee
Xilinx Employee
15,078 Views
Registered: ‎01-03-2008

Re: Virtex 5 damage concerns if one powers I/O but leaves core voltage off for a long time

The HWSAP_EN won't work without VCCINT and probably VCCAUX.

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Xilinx Employee
Xilinx Employee
15,077 Views
Registered: ‎01-03-2008

Re: Virtex 5 damage concerns if one powers I/O but leaves core voltage off for a long time

> so that if the core is "off" then I/O defined as inputs could even possibly become outputs?

 

Yes, the I/O can actively drive if the VCCINT and VCCAUX are not brought up before VCCO. Here is the relevant section from the Virtex-5 data sheet, DS202.

 

The power supplies can be turned on in any sequence,
though the specifications shown in Table 5 are for the
recommended power-on sequence of VCCINT, VCCAUX, and
VCCO. The I/O will remain 3-stated through power-on if the
recommended power-on sequence is followed. Xilinx does
not specify the current or I/O behavior for other power-on
sequences.

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