Hi, I'm facing some timing related issues on a virtex6 based design.
We've designed a full custom digital board which includes a xc6vlx240 FPGA and two AD9284 dual channel analog device 8 bit ADCs operating at 250 MHz and using DDR data transfer.
On a test version based on lm605 development board and an ADc evaluation board connected to the FPGA trough the FMC connector of the LM605 I had both ADC data output clocks connected to innercolumn clock capable pins. I used therefore a deskew PLL to match the timing of the IDDR data (from the ADC) at the FPGA input. Timing was met end everything was working properly.
On the new design unfortunately one of the ADCs are placed at an outercolumn clock capable clock pin which cant be routed to a bufg and I'm not able anymore to close the timing.
Seeking around on this forum I had the impression that the cleanest and best way for solving the problem is to use the approach in which the ddr input clock is locally directly feed to the iddr cell trough an zero tap IODELAYEI and BUFIO of the same IO bank. The input data is routed to the IDDR data input trough an IODELAYE1 too.
The output data from the IDDR is connected to a small clock bridge FIFO whose write clock comes from a BUFR connected to the IODELAYE1 DDR clock as reported in the attached pdf .
This approach looks reasonable to me but it seems impossible to meet timing whatever data IODELAY I set (constant).
In the attached pdf I also reported the timing constrain I'm using just for double check. Data and clock signal path are length matched (on PCB).