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Registered: ‎10-20-2010

Virtex-6 GTX MGTREFCLK Phase adjustment



in an existing design of two FPGAs connected through GTX transceivers, device A (TX_CLK_SOURCE: TX_PLL) has a free running MGTREFCLK. Device B (TX_CLK_SOURCE: RXPLL) has a tuneable PLL chip at the input to the MGTREFCLK pins of the FPGA. Device B compares the phase of the generated MGTREFCLK and RXRECCLK internally and tunes the phase of MGTREFCLK accordingly.

This works well, and the two devices do not need any other connection as the data lines to operate the GTX connection.


My question is now wether it is possible to achieve the same operation without the need of an externally tuneable PLL chip for device B. With my current state of information, it is not possible to influence the MGTREFCLK on the way to the GTX receiver (besides the IBUFDS_GTXE1), so there is no possibility to insert a clock manager with phase shift ports to tune the supplied clock.

Is there any other possibility to either tune the MGTREFCLK or is there a completely other way to operate Device B's GTX receiver without the need of connecting any other than the data lines of the GTX to Device A? (Like -just an idea- tuning the phase of TXOUTCLK to match RXRECCLK and feed it into TXUSRCLK2 and RXUSRCLK2 or something like that?)


Thank you for your answers!

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Xilinx Employee
Xilinx Employee
Registered: ‎01-03-2008

The system that you describe is a synchronous communication link between two end points and this is how a SONET link would function.


If your system does not have a master source and a slave source that is clocked from cleaned up version of the RX recovered clock then you have 3 choices.


1) Use a protocol that supports 8b10b clock correction so that the receiver can compensate for clock frequency difference 

2) Maintain two different clock domains one for the TX path and one for the RX that uses the RXRECCLK.

2) Except the fact that you will have errors when the RX elastic buffer either underflows or overflows 



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