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davecowl
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Registered: ‎08-26-2011

Virtex 6 IBIS Files - no [Receiver Thresholds]?

 

When I simulate my DDR3 interface from the Virtex 6 with Hyperlynx I get the message that the models have no [Receiver Thresholds] section. These models were generated using ibiswriter.

 

Also of note, bidirectional DQ lines do not have a [Model Selector] to allow me to select the DCI if it is input and regular driver if it is output. I created my own [Model Selector] section to allow me to switch modes in the simulation and that works ok. 

 

Is there any suitable resolution for the missing [Receiver Thresholds]?

 

Thanks! Dave.

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jfundora
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Registered: ‎04-09-2012

The same thing for me for Spartan 6.  From my understanding so far, this section is specific for how the FPGA is set up and how MIG is set-up.  Trying to figure more out, but all I know is that Micron has this section in there IBIS model and Hyperlynx yells at you if you don't have this in your IBIS model for your FPGA.  Are there generic values that can be used or steps on how to figure out your specific configuration for the FPGA?  Any help would be great! Thanks!!

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davecowl
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Registered: ‎08-26-2011

I have been able to create the specific IBIS from the .ncd file using ibiswriter. I think I just used the default settings. Hyperlynx certainly prefers to have the [Receiver Thresholds] though it runs with the Vinh and Vinl defined in the IBIS if they are not there.

 

I am getting closer to having completed simulations based on the simpler Vinh and Vinl...

 

Something to watch for is having the simulation probe at the die rather than the pin. This required modification to both the FPGA and Micron IBIS files for me. Something like:

 

|
[Component] VIRTEX-6
Timing_location Die
[Manufacturer] Xilinx Inc.
[Package]
|FF1156

 

 where 'Timing_location Die' was manually added.

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stuartnthomson
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Registered: ‎11-18-2010

I'm having similar trouble too. I've generated the design-specific ibs file using ibiswriter, but I don't have an .ncd to work with as yet so this has been limited to pin definitions and IO Standards so as to be compatible in the Hyperlynx environment.

 

I don't get the [Model Selector] sections for the various functions (e.g. DDR3_DATA, DDR3_ADDRESS) which enables the ODT controller.

 

As a result, the simulation won't run and I get a number of warning mainly due to the DQ lines only being defined as inputs (can't seem to set these as IO), Receiver Threshold warnings, as well as the Model Selector issues too.

 

I have an example of a good (non-Xilinx) ibs file of a DDR3 Controller and it has many more Model parameters (e.g. DDR3 Data I/O, 1x, DDR3 Data I/O, 1x with ODT60, 60 Ohm ODT Input etc.) How do I get an equivalent Virtex-6 one? Is this something I need to generate or does this already exist somewhere?

 

I've logged this with Mentor who say the problem lies with the DDR3 Controller, which in this case is the Virtex-6 (SX315T). To this end, I need a better model, suitable for use in DDRx simulations.

 

Thanks

Stuart 

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pjrajda
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Registered: ‎07-10-2013

I have the same problem - how did you resolved yours?

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saddam.sarwar
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7,041 Views
Registered: ‎10-20-2013

hey guys!!!

i need .hyp file for virtex 5 board for my final year project. i will be very thankful to you if you arrange for me. 

thanks

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