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Adventurer
Adventurer
5,843 Views
Registered: ‎04-02-2010

Virtex 6 IO not active but done pin asserts after configuration

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I have a Virtex6 (xc6vsx315t) on my board that has in intermittent FPGA configuration issue.  The DONE pin asserts after configuration, but from what I can tell the IO banks (1.5V) sometimes do not become active.  When I have an chipscope ILA in the bitstream I am able to communicate to it properly with JTAG (2.5V IO), but the 1.5V IO seems to sometime not become active.

 

A random guess is a problem related to the GTS deassertion but I have no understanding of a mechanism that would cause this to fail.  The settings for the startup sequence are the following:

DONE_cycle: 4

GTS_cycle: 5

GWE_cycle: 6

 

Has anyone seen this issue or know of a possible cause for this behavior?  I appreciate any help you can give

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Adventurer
Adventurer
10,438 Views
Registered: ‎04-02-2010

Thanks for the insights on this issue.

View solution in original post

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Scholar
Scholar
5,837 Views
Registered: ‎02-27-2008

GTS, GWE are global:

 

They affect all IO (and GWE affects all storage elements - FF).

 

If the 1.5v IO appears affected, that would be the 1.5 volt Vcco power supply, or its connections to the device.


DONE is asserted as long as the Vcco for configuration is above the shut down value (~ 0.6 v).  So a mad power supply may not prevent DONE from going high.

Austin Lesea
Principal Engineer
Xilinx San Jose
Adventurer
Adventurer
5,745 Views
Registered: ‎04-02-2010

Thanks for the quick reply.  That information about the global nature of GTS and GWE clarified an issue for me.  I now see all the steps of configuration must have completed since GWE allows chipscope to work.

 

Looking at the 1.5V IO, I cannot see any issues with it.  It is definitely 1.5V.  The only other thought I had was a possible transient on a power supply (Vcco or Vccaux) during the configuration that I messes things up.  I haven't been able to catch anything on an oscilloscope, but do you know of any things like that which seem to make since for what I've described?

 

Regards,

David

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Scholar
Scholar
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Registered: ‎02-27-2008

David,

 

A glitch that affects just one IO bank, and all the others not?  I see no way for this to occur.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Adventurer
Adventurer
10,439 Views
Registered: ‎04-02-2010

Thanks for the insights on this issue.

View solution in original post

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