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Visitor h_sotoudi
Visitor
14,179 Views
Registered: ‎01-20-2014

Virtex 6 MMCM input clock source problem

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Hi,

 

I have designed a board using Virtex6 LX75T and 4 high speed DACs. I connected each DAC to one of FPGAs io Bank and I have used MRCC pins as clock input for MMCM ( differential) and 4 pins for off chip feedback. Unfortunately I connected Bank16 to one DAC and after designing I found that it is not possible to drive MMCM via Bank16 because it is not next to MMCM and I have error while translating so what is the solution to solve the problem? I know that I can use CLOCK_DEDICATED_ROUTE = False but is there any better solution or not?

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Xilinx Employee
Xilinx Employee
21,954 Views
Registered: ‎09-20-2012

Re: Virtex 6 MMCM input clock source problem

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Hi,

 

This new error is because of restriction on IOB/BUFG placement.

 

The CCIO can drive the BUFG which is located in same half as that of CCIO. Try locking the BUFG instance to top half of the device. The top half BUFG includes sites from BUFGCTRL_X0Y16 to BUFGCTRL_X0Y31.

 

Below is example of UCF constraint to lock this BUFG instance.

 

INST "DAC1_interface/BUFG_in_mmcm" LOC = BUFGCTRL_X0Y16;

 

Also I see that you have added BUFG to only one set of IOB/MMCM. Add BUFG to other set of IOB/MMCM (CCIO D27).

 

Thanks,

Deepika.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
14,170 Views
Registered: ‎09-20-2012

Re: Virtex 6 MMCM input clock source problem

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Hi,

 

Can you show us the error message?

 

Thanks,

Deepika.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
14,162 Views
Registered: ‎08-01-2012

Re: Virtex 6 MMCM input clock source problem

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Please check whether the IO standard is same for both sides of interface (Driver and receiver) or not. Also check the timings (set-up and hold times etc) matching or not?

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Visitor h_sotoudi
Visitor
14,146 Views
Registered: ‎01-20-2014

Re: Virtex 6 MMCM input clock source problem

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ERROR:Place:1155 - A clock IOB / MMCM clock component pair have been found that are not placed at an optimal clock IOB /
   MMCM site pair. The clock IOB component <DAC1_FBin_P> is placed at site <D27>. The corresponding MMCM component
   <DAC1_interface/MMCM_BASE_inst> is placed at site <MMCM_ADV_X0Y5>. The clock IO can use the fast path between the IOB
   and the Clock Manager if a) the IOB is placed on a Local Clock Capable IOB site in the same horizontal clock region
   pair as the MMCM site (fastest dedicated path), or b) the IOB is placed on a Global Clock Capable IOB site which has
   a dedicated fast path to all MMCM sites. You may want to analyze why this problem exists and correct it. If this sub
   optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to
   demote this message to a WARNING and allow your design to continue. However, the use of this override is highly
   discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in
   the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used
   directly in the .ucf file to override this clock rule.
   < NET "DAC1_FBin_P" CLOCK_DEDICATED_ROUTE = FALSE; >
   < PIN "DAC1_interface/MMCM_BASE_inst.CLKFBIN" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Place:1155 - A clock IOB / MMCM clock component pair have been found that are not placed at an optimal clock IOB /
   MMCM site pair. The clock IOB component <DAC1clk_inP> is placed at site <B27>. The corresponding MMCM component
   <DAC1_interface/MMCM_BASE_inst> is placed at site <MMCM_ADV_X0Y5>. The clock IO can use the fast path between the IOB
   and the Clock Manager if a) the IOB is placed on a Local Clock Capable IOB site in the same horizontal clock region
   pair as the MMCM site (fastest dedicated path), or b) the IOB is placed on a Global Clock Capable IOB site which has
   a dedicated fast path to all MMCM sites. You may want to analyze why this problem exists and correct it. If this sub
   optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to
   demote this message to a WARNING and allow your design to continue. However, the use of this override is highly
   discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in
   the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used
   directly in the .ucf file to override this clock rule.
   < NET "DAC1clk_inP" CLOCK_DEDICATED_ROUTE = FALSE; >
   < PIN "DAC1_interface/MMCM_BASE_inst.CLKIN1" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
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Xilinx Employee
Xilinx Employee
14,135 Views
Registered: ‎09-20-2012

Re: Virtex 6 MMCM input clock source problem

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Hi,

 

The D27,B27 are CCIO pins. The CCIO pins which are in inner IO column are alone capable of driving MMCM directly. The D27 and B27 are not in inner IO column. Hence the error. You can find this info in page-26 of UG362 http://www.xilinx.com/support/documentation/user_guides/ug362.pdf .

 

Try inserting a BUFG in between CCIO pin and MMCM and see if that helps.

 

Thanks,

Deepika. 

Thanks,
Deepika.
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Visitor h_sotoudi
Visitor
14,123 Views
Registered: ‎01-20-2014

Re: Virtex 6 MMCM input clock source problem

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Dear Deepika,

 

it doesn't work by putting BUFG :-)

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Xilinx Employee
Xilinx Employee
14,120 Views
Registered: ‎09-20-2012

Re: Virtex 6 MMCM input clock source problem

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Hi,

 

Ok, is it the same error after inserting bufg?

Thanks,
Deepika.
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Visitor h_sotoudi
Visitor
14,113 Views
Registered: ‎01-20-2014

Re: Virtex 6 MMCM input clock source problem

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this is with BUFG

 

ERROR:Place:1153 - A clock IOB / BUFGCTRL clock component pair have been found that are not placed at an optimal clock
   IOB / BUFGCTRL site pair. The clock IOB component <DAC1clk_inP> is placed at site <B27>. The corresponding BUFGCTRL
   component <DAC1_interface/BUFG_in_mmcm> is placed at site <BUFGCTRL_X0Y9>. The clock IO can use the fast path between
   the IOB and the Clock Buffer if a) the IOB is placed on a Global Clock Capable IOB site that has the fastest
   dedicated path to all BUFGCTRL sites, or b) the IOB is placed on a Local Clock Capable IOB site that has dedicated
   fast path to BUFGCTRL sites in its half of the device (TOP or BOTTOM). You may want to analyze why this problem
   exists and correct it. If this sub optimal condition is acceptable for this design, you may use the
   CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to
   continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is
   recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock
   placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule.
   < NET "DAC1clk_inP" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Place:1155 - A clock IOB / MMCM clock component pair have been found that are not placed at an optimal clock IOB /
   MMCM site pair. The clock IOB component <DAC1_FBin_P> is placed at site <D27>. The corresponding MMCM component
   <DAC1_interface/MMCM_BASE_inst> is placed at site <MMCM_ADV_X0Y1>. The clock IO can use the fast path between the IOB
   and the Clock Manager if a) the IOB is placed on a Local Clock Capable IOB site in the same horizontal clock region
   pair as the MMCM site (fastest dedicated path), or b) the IOB is placed on a Global Clock Capable IOB site which has
   a dedicated fast path to all MMCM sites. You may want to analyze why this problem exists and correct it. If this sub
   optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to
   demote this message to a WARNING and allow your design to continue. However, the use of this override is highly
   discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in
   the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used
   directly in the .ucf file to override this clock rule.
   < NET "DAC1_FBin_P" CLOCK_DEDICATED_ROUTE = FALSE; >
   < PIN "DAC1_interface/MMCM_BASE_inst.CLKFBIN" CLOCK_DEDICATED_ROUTE = FALSE; >
 
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
 
 
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Xilinx Employee
Xilinx Employee
21,955 Views
Registered: ‎09-20-2012

Re: Virtex 6 MMCM input clock source problem

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Hi,

 

This new error is because of restriction on IOB/BUFG placement.

 

The CCIO can drive the BUFG which is located in same half as that of CCIO. Try locking the BUFG instance to top half of the device. The top half BUFG includes sites from BUFGCTRL_X0Y16 to BUFGCTRL_X0Y31.

 

Below is example of UCF constraint to lock this BUFG instance.

 

INST "DAC1_interface/BUFG_in_mmcm" LOC = BUFGCTRL_X0Y16;

 

Also I see that you have added BUFG to only one set of IOB/MMCM. Add BUFG to other set of IOB/MMCM (CCIO D27).

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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Visitor h_sotoudi
Visitor
14,107 Views
Registered: ‎01-20-2014

Re: Virtex 6 MMCM input clock source problem

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what do you mean by locking BUFG instance? you mean that it dependce on synthesizing process and put BUFG in other sites that is not related to this bank.

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Xilinx Employee
Xilinx Employee
13,627 Views
Registered: ‎09-20-2012

Re: Virtex 6 MMCM input clock source problem

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Please check my earlier response.

Thanks,
Deepika.
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Visitor h_sotoudi
Visitor
13,626 Views
Registered: ‎01-20-2014

Re: Virtex 6 MMCM input clock source problem

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Dear Deepika,

 

Thank you very much for your help. I will try this way and will write about consequnces.

 

Best,

Hamed

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Visitor h_sotoudi
Visitor
13,624 Views
Registered: ‎01-20-2014

Re: Virtex 6 MMCM input clock source problem

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Hi,

 

This is the result of locking BUFG

 

ERROR:Place:1153 - A clock IOB / BUFGCTRL clock component pair have been found that are not placed at an optimal clock
   IOB / BUFGCTRL site pair. The clock IOB component <DAC1clk_inP> is placed at site <B27>. The corresponding BUFGCTRL
   component <DAC1_interface/BUFG_in_mmcm> is placed at site <BUFGCTRL_X0Y23>. The clock IO can use the fast path
   between the IOB and the Clock Buffer if a) the IOB is placed on a Global Clock Capable IOB site that has the fastest
   dedicated path to all BUFGCTRL sites, or b) the IOB is placed on a Local Clock Capable IOB site that has dedicated
   fast path to BUFGCTRL sites in its half of the device (TOP or BOTTOM). You may want to analyze why this problem
   exists and correct it. If this sub optimal condition is acceptable for this design, you may use the
   CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to
   continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is
   recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock
   placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule.
   < NET "DAC1clk_inP" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Place:1155 - A clock IOB / MMCM clock component pair have been found that are not placed at an optimal clock IOB /
   MMCM site pair. The clock IOB component <DAC1_FBin_P> is placed at site <D27>. The corresponding MMCM component
   <DAC1_interface/MMCM_BASE_inst> is placed at site <MMCM_ADV_X0Y1>. The clock IO can use the fast path between the IOB
   and the Clock Manager if a) the IOB is placed on a Local Clock Capable IOB site in the same horizontal clock region
   pair as the MMCM site (fastest dedicated path), or b) the IOB is placed on a Global Clock Capable IOB site which has
   a dedicated fast path to all MMCM sites. You may want to analyze why this problem exists and correct it. If this sub
   optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to
   demote this message to a WARNING and allow your design to continue. However, the use of this override is highly
   discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in
   the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used
   directly in the .ucf file to override this clock rule.
   < NET "DAC1_FBin_P" CLOCK_DEDICATED_ROUTE = FALSE; >
   < PIN "DAC1_interface/MMCM_BASE_inst.CLKFBIN" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
 
thanks,
Hamed
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Xilinx Employee
Xilinx Employee
13,617 Views
Registered: ‎09-20-2012

Re: Virtex 6 MMCM input clock source problem

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Hi Hamed,

Can you tell me the complete part you were using?

Is it possible to share the test case so that I can take a look?

Thanks,
Deepika
Thanks,
Deepika.
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Visitor h_sotoudi
Visitor
13,611 Views
Registered: ‎01-20-2014

Re: Virtex 6 MMCM input clock source problem

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Dear Deppika,

 

I will provide a simple code and a description of hardware  and will send it to you. Thank you very much for your help and time.

 

Best regards,

Hamed.

 

 

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Visitor h_sotoudi
Visitor
13,607 Views
Registered: ‎01-20-2014

Re: Virtex 6 MMCM input clock source problem

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Dear Deepika,

 

The source code is attached. The hardware as I explained is DACs which is connected to FPGA and the clock scheme is as follow:

 

One clock is provided from DAC to FPGA and is connected to MRCC pins in differential mode. This clock is connected to MMCM module in FPGA and MMCM should drive DAC clock pin which is equal to data port in size. There is one external feedback for each MMCM. This off chip feedback drives MMCM through SRCC pins but output pins are normal IO pins.

 

Best,

Hamed

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Xilinx Employee
Xilinx Employee
13,594 Views
Registered: ‎09-20-2012

Re: Virtex 6 MMCM input clock source problem

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Hi Hamed,

 

Which version of ISE are you using?

 

Can you attach the ISE project archive?

 

In ISE GUI, go to Project --> Archive. This creates archive at selected location. Please attach this project archive.

 

I got below error in ISE 14.6 

 

Place:1500 - The component DAC1_interface/MMCM_BASE_inst belongs to a RPM (its structure is printed below) with 4 instances in the design, and there are only 2 suitable sites to place such RPMs in the device.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Visitor h_sotoudi
Visitor
13,587 Views
Registered: ‎01-20-2014

Re: Virtex 6 MMCM input clock source problem

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Hi deepika,

 

The archive file is attached. Please find it. The version of ISE is 13.2

 

Best,

Hamed

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Xilinx Employee
Xilinx Employee
13,573 Views
Registered: ‎09-20-2012

Re: Virtex 6 MMCM input clock source problem

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Hi,

 

The IO's in inner column can alone drive BUFG. You have IO's locked to outer IO columns which cannot directly drive BUFG/MMCM. They can drive BUFR/BUFIO. This is documented in the same page of UG mentioned earlier. Sorry I missed this out earlier.

 

When I replaced the BUFG instantiations (BUFG_FB_mmcm,BUFG_FB_inst) with BUFR instantiations in DACpin.v file, it passed Implementation. Check is this suits your requirement.

 

Thanks,

Deepika.

 

 

Thanks,
Deepika.
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Visitor h_sotoudi
Visitor
13,560 Views
Registered: ‎01-20-2014

Re: Virtex 6 MMCM input clock source problem

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Dear Deepika,

 

Thank you very much for your help and time.

 

Best,

Hamed

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