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Highlighted
4,294 Views
Registered: ‎06-11-2012

Virtex-6 PROGRAM_B to INIT_B timing

What is the timing relationship between PROGRAM_B going low and INIT_B going low?

 

--Brad

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Instructor
Instructor
4,290 Views
Registered: ‎07-21-2009

Re: Virtex-6 PROGRAM_B to INIT_B timing

Some time (unspecified) after PROGRAM_B is asserted LOW, INIT_B will be forced LOW.  INIT_B will remain LOW until some time after PROGRAM_B is de-asserted HIGH.

 

Other than a minimum (LOW) pulse width for PROGRAM_B (DS152, Table 59), I don't see a spec for min or max delay from PROGRAM_B (LOW) to INIT_B (LOW) in either DS152 or UG360.  There is a spec (TPL) for PROGAM_B (HIGH) to INIT_B (HIGH): 5mS (max).

 

You may need to open a webcase to get the specification you need (if available) from Xilinx tech support.

 

-- Bob Elkind

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Scholar
Scholar
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Registered: ‎02-27-2008

Re: Virtex-6 PROGRAM_B to INIT_B timing

Brad,

 

Such timing is typically not characterized, as it is unimportant.  Why do you need it?  What is it you are trying to do?

 

If you are trying to program the part using a microprocessor, and rather than looking at the INIT_b pin to see that the device is ready, you just wish to do a simple wait:  do not do that!  Always verify the next step, and never use a default wait instead of looking to see if the device is ready.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Teacher
Teacher
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Registered: ‎09-09-2010

Re: Virtex-6 PROGRAM_B to INIT_B timing

Apologies for butting in, but shouldn't there be some sort of absolute worst-case time to permit setting up a watchdog or similar exception handling?

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"If it don't work in simulation, it won't work on the board."