Virtex-I reconfiguration/readback weird problem with JBits
I am experiencing the following problem. I use a custom controller i created to act as an interface between the PC and a target XCV1000 device to be configured over JTAG at a max JTAG_CLK of 25MHz. All configuration/reconfiguration bitstreams are created by JBits 2.8 and so are expected to be correct.
When i perform a full or partial configuration , the DONE pin remains always high.
However, there appears to be a problem regarding the configuration process. In the last CLB column or set of frames in the last individual column being configured has a frame with all zeroes, compared to the original bitstream.
Due to the mapping of my design, a full configuration does not produce an error in the design's operation. However, when a partial reconfiguration on a LUT is performed (let's call it LUT1) even with the original LUT value, the entire design produces wrong outputs. This erroneous behaviour is masked when a LUT (let's call it LUT2) in the highest MJA address values is configured. At this point, the all-zeroes frames migrates to the column associated with the MJA of LUT2. If i try the same with a LUT2 placed in a very low MJA (close to 1), then the design behaves the same as in the single LUT1 partial reconfiguration case, since the frames of LUT1 will appear last at the partial bitstream.
Erroneous outputs are always consistent indicating there is no random bit flip in the configuration process due to noise.
Could there be a problem with the pipe flushing process ? Could anyone suggest a way to correct or overcome this problem?