05-09-2014 12:05 PM
The UltraScale clocking guide (UG572--Dec 2013) describes the new CMT's with 1 MMCM and 2 PLLs. It even notes that: "The PLL’s primary purpose is to provide clocking to the PHY I/Os."
But that clocking guide does not talk about I/O DLL's and Fractional PLL's mentioned on the product table:
So as I read it, an XCVU080 is going to have 16 CMT's--which means 32 PLL's--and 64 DLL's. That is a lot of clocking resources for I/O. What about clock deskew (aka, clock feedback)? Are only the 16 MMCM's able to do clock deskew?
Is there another guide available so we can read more about DLL's and fractional PLL's?