09-15-2009 12:42 PM
I want to connect the Clock Capable (CC) I/Os to an external clock and drive some other I/Os of the Virtex 4.
Is there some constraints for it?
I means it is possible to drive any I/Os of that FPGA.? How?
09-17-2009 03:26 AM
Not sure if I understand your questions. Virtex4 has 3 IO columns. Avoid using the CC IOs in the center IO column. Also keep in mind that CC IOs can only drive IOs/logic in up to 3 clock regions.
09-17-2009 04:41 AM
Thanks for your replay.
How is the relation between IO columns, IO bank, clock region?
What do you mean with 3 clock regions? 3 neighbourhood clock regions or 3 any clock regions?
09-17-2009 08:10 PM
Please take a look at the "Regional Clock Resources" section of the Virtex4 user guide (http://www.xilinx.com/support/documentation/user_guides/ug070.pdf) . Please ask if you still have questions after reading it.