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Visitor
Visitor
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Registered: ‎05-19-2009

What behavior/stress would occur if Vcco incorrectly connected to 2.5V instead of 3.3V?

I have a board with 3.3V LVTTL inputs and outputs.  External logic drives/expects 3.3V and the FPGA image was designed for 3.3V (IOSTANDARD=LVTTL).  However, the bank's Vcco is incorrectly wired to 2.5V.  How would the I/O be expected to perform?

 

1. Would the outputs just drive to a lower Voh?  Instead of reaching 3.3V or so, would they max out around 2.5V?  If so, provided little loss to the receiver, I think it could still see the 2.0 Vih required to operate properly.

2. Would the Xilinx input receiver be overstressed by receiving 3.3V when Vcco is only 2.5V?

 

Thanks,

  Steve

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