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Visitor
Visitor
13,356 Views
Registered: ‎04-18-2014

Why do the XC5VSX95T can not output clk2x, but can output clkFx?

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Hi,the input of the clock is 50MHz, use the DCM to output clk2x(100MHz) and clkFx(20MHz). The clock of clkFx(20MHz) can work well , but the clk2x(100MHz) can not work, and the locked signal is low. why??

Thanks!

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Visitor
Visitor
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Registered: ‎04-18-2014
sorry! the test pin is wrong, this is the problem! Thank you very much!! if the input clk is 20 MHz, how can I get the clkFx, which is 100 MHz.

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Moderator
Moderator
13,353 Views
Registered: ‎01-15-2008

can you check if the reset to the DCM is properly given.

Check the following link for the clocking debug guide 

http://www.xilinx.com/support/troubleshoot/clocking_debug.htm

 

--Krishna

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Xilinx Employee
Xilinx Employee
13,352 Views
Registered: ‎04-16-2012

Hi,

 

Are you observing this behavior in simulation or hardware?

If it is in simulation, observe there are any warnings that are printed in simulation log?

 

If it is in hardware, run the post-route simulation and see whether you are locked signal is HIGH?

 

Thanks,

Vinay

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Moderator
Moderator
13,346 Views
Registered: ‎01-16-2013
Hello,

Please ensure that DCM feedback you have provided correctly?

Thanks,
Yash
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Moderator
Moderator
13,340 Views
Registered: ‎02-16-2010
Are you using DCM through instantiation. Where are you observing the issue? in simulation/hardware?

20MHz at clkFx output is not in the range of DCM.
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Xilinx Employee
Xilinx Employee
13,292 Views
Registered: ‎07-31-2012

Hi,

 

Please note that there is a minimum and maximum range for the DCM outputs. Check the V-5 datasheet Pg 57 table 76 - http://www.xilinx.com/support/documentation/data_sheets/ds202.pdf for the valid ranges.

 

For the CLK2X, in High Frequency Mode the minimun range is 240MHz. Probably that is the reason why you are unable to find the output. Check the value of the Parameter DFS_FREQUENCY_MODE.

 

• 0 for low frequency mode
• 1 for high frequency mode

 

dcm.PNG

 

Thanks,
Anirudh

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Visitor
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Registered: ‎04-18-2014
thanks. if the input clk is 20 MHz, I want to get the clkFx ,which is 100MHz , How to do this??
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Visitor
Visitor
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Registered: ‎04-18-2014
sorry! clkFx should be clkDx, if the input clk is 20 MHz, how can I get the clkFx, which is 100 MHz.
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Xilinx Employee
Xilinx Employee
13,278 Views
Registered: ‎07-31-2012

Hi,

 

Please use the SelectIO WIzard to generate the core with these settings for V-5. The tool should write the settings for you.

 

Thanks,
Anirudh

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Visitor
Visitor
13,277 Views
Registered: ‎04-18-2014
the feedback is internal
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Visitor
Visitor
18,162 Views
Registered: ‎04-18-2014
sorry! the test pin is wrong, this is the problem! Thank you very much!! if the input clk is 20 MHz, how can I get the clkFx, which is 100 MHz.

View solution in original post

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Xilinx Employee
Xilinx Employee
9,185 Views
Registered: ‎07-31-2012

Hi,

 

In low frequency mode the CLKIN supports 20MHz input. And the DFS output also supports 100MHz as it is in the range 32-180 as per the table.

 

As said use the Clocking wizard to do this. Let me know if you need help with the Clocking Wizard.

 

However check the attributes which i mentioned previously to set the high frequency and low frequency mode.

 

In case you are doing it manually 

 

Set this attribute DFS_FREQUENCY_MODE as low as given in Pg 60  http://www.xilinx.com/support/documentation/user_guides/ug190.pdf and give the input clock 20MHz and output clock through CLKFX as 100MHz.

 

 

 

 

Thanks,
Anirudh

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