01-19-2010 01:10 PM
I am looking for any guidance on how to "fake" out the electrical requirements to DC couple a LVDS transmitter at 1.8V to a Virtex-5 IO.
At the moment, I am thinking of enabling the Virtex I/O with a DIFF_HSTL_I_DCI_18 I/O configuration VREF will be set to 0.95V, VRN through 100 ohms to ground, VRP through 100 ohms to VCCO.
01-19-2010 02:07 PM
LVDS is a standard, with a specified Vcm, and Vdiff. It is no different when you power the interface chips from 1.8, 2.5 or 3.3v (if they are standard drivers and receivers, the Vcc does not matter -- as long as it is what is specified for those chip).
So, a 1.8v powered standard LVDS driver chip (not a Xilinx product) drives any LVDS standard interface, regardless of the Vcc to that chip.
In the case of V5, the Vcco = 2.5 v for proper LVDS operation.
01-20-2010 09:02 AM
Thanks for replying.
So if I understand your comments, I can take a 1.8v powered standard LVDS driver chip (not a Xilinx product), and drive Xilinx LVDS_25 receiver.
So you are saying that both driver and receiver have common Vref levels.
08-31-2010 04:11 AM
We are Developing one product in that we are using the Spartan 3AN XC3S400AN FGG400 -4C, In this would like to interface the Xilinx FPGA to a High Speed ADC using LVDS interface
1. Xilinx FPGA LVDS specifies the Voltage Levels of 2.5V & 3.3V as like LVDS25 & LVDS33
2. High speed ADC(ADS62P29) Specifies the Voltage Levels of 1.8V
So we would like to confirm that this interface will work fine without any issue?
Also we would like to know if any additional circuit needs to be added in the design
Please replay at earliest as its very critical phase of our design
Anticipating the needful
Thanks & Regards
08-31-2010 08:20 AM
Honestly, the only way that you can be sure is to run the simulations. Download our IBIS models (http://www.xilinx.com/support/download/index.htm)
Run the simulation and verify that everything matches up correctly. If you are worried about your design not matching up properly, simulation is the only option that you can use to be sure.
08-31-2010 08:27 AM
I have already stated (many times) LVDS is a standard, and if both chips comply, then connecting them works (regardless of Vcc).
And Carl, you are right: simulation will show it works. IBIS is as good as hspice in this case, so a Hyperlynx sim of the ADC connected to the FPGA will also tell if this will work. Xilinx hspice and IBIS models are as good as a data sheet number: they are guarantees of performance.
The key is: is the ADC LVDS standard, or not?
02-18-2011 10:41 AM
On Virtex6 devices, LVDS_25 is the only LVDS IO standard listed in the user guide. Note (1), in UG361 says that "differential inputs and inputs using VREF are powered from VCCAUX...". I believe this means that LVDS_25 can be instantiated for LVDS reception in a bank with 1.8V VCCO, for instance, because LVDS will not exceed this VCCO. Can you confirm that this is the correct interpretation? If this is false, it is not apparent how to instantiate an LVDS receiver in a non-2.5V bank on V6 due to lack of any other LVDS IO type besides LVDS_25.
For reference, I am considering the converse situation as the grandparent post -- I would like to receive any LVDS-compliant signal in a bank that may not have VCCO set to 2.5V. The LVDS driver feeding my FPGA bank may be operating off a 1.8, 2.5, or 3.3V supply, but will generate an LVDS-standard signal.
02-18-2011 10:57 AM
Not sure what you are reading: V6 MUST use 2.5v Vcco for LVDS_25.
Page 84 (among others)
02-18-2011 11:45 AM
> I believe this means that LVDS_25 can be instantiated for LVDS reception in a bank with 1.8V VCCO,
> for instance, because LVDS will not exceed this VCCO. Can you confirm that this is the correct interpretation?
Yes, an IBUFDS_LVDS_25 or an IBUFDS with an IOSTANDARD property of LVDS_25 can be placed in a 1.8V or 2.5V bank and potentially a 1.5V if you can guarantee that the voltage on the pins will not exceed the 1.5V VCCO.
Table 1-33 in UG361 has this information.
02-18-2011 11:57 AM
It also says that it you need the internal termination, the 100 ohms is only guaranteed to be within the tolerance for Vcc=2.5v.
I think this is very confusing...
The footnote referred to only implies that the differential input is powered from Vccaux, it doesn't mention that when Vcco=1.8v all standards are met. And yet, there is anote that the internal termination may not meet spec if the Vcco isn't 2.5v. If the internal termination is part of the receiver, then it is powered from Vccaux....
Of course, the voltages into the LVDS + and - inputs can not be greater than those allowed when Vcco=1.8 volts for reasons of relaibility. But, does the LVDS standard ranges for the + and - outputs fall within our allowed range? If not, we shouldn't suggest connection to an LVDS_25 input powered by 1.8v.
02-18-2011 12:31 PM - edited 02-18-2011 12:32 PM
Austin, I'm not sure what you are confused about.
The LVDS_25 input can be used with a VCCO of 1.8 and 2.5V in Virtex-6 (or lower the input voltage never exceeds the VCCO level, a sub-LVDS output would be an example where a lower voltage could be used)
Using the internal DIFF_TERM option requires that the VCCO of the bank be 2.5V as noted in UG361, so if you are using any other VCCO level simply use an external 100ohm termination resister.
02-18-2011 01:07 PM
OK. If we just said what you just did, I am sure there would be no diffculty, but ug361 isn't as easy to understand (for me).
02-18-2011 01:21 PM - edited 02-18-2011 01:22 PM
...but ug361 isn't as easy to understand (for me).
Austin, perhaps you should open a webcase for this? :) (you knew this was coming when you wrote it, right?)
- Bob Elkind
02-18-2011 01:37 PM - edited 02-18-2011 01:39 PM
austin.lesea : I was referring to Table 1-33, page 87 of UG361, as mcgett discovered.
Thanks for the good input. I had not considered the variance in the value associated with diffterm as a function of VCCO. Using an external 100Ohm termination resistor does seem to be the bulletproof choice. We're looking into specifications on the variance of diffterm value as a function of VCCO to see if that is also a viable option.
-- edit --
I see that austin indicates the diffterm will not be in spec for VCCO != 2.5V. We're keeping that in mind while we work on this, planning to default to external termination.
02-18-2011 02:15 PM
If you obtain the hspice model (encrypted) you can simulate exactly what will happen over process corners, temperature, and voltage to this 'resistor.' I suspect it is highly non-critical. If you place anywhere from 50 to 200 ohms termination in the simulator of the signal integrity, I doubt it makes any difference.
But data sheets are data sheets, and spec are specs: I understand we can't claim standards compliance over too many variables varying.
I think we can get overly obsessed with details. Signal integrity is important, and it needs to be verified, but matching +/- .x ohm is never required....
I think you gain a lot from use of the internal resistor primarily because there is no capacitive or inductive elements at play: it is just a lot cleaner. If it were me, I would find a way to continue to use the internal termination (simulate, find where it breaks, and then avoid going to that place).