Writing ADC data into DDR3RAM using Virtex7 fpga (vhdl)

[dare_bandom]

I have data sampled in an ADC 337.5 MHz.I want to write that data into DDR3RAM using Virtex-7 fpga.(Why ?) use fpga is it is an existing architecture and there is no direct interface between adc & ddr3ram & i can't change design at this stage.

My progress: To write data from Virtex 7 to DDR3 RAM, i used memory controller ip core given by vivado tool.After designing this,i need to give data from ADC to this memory controller module(some sort of interface).

Figure1 which shows 7 Series FPGAs Memory Interface Solution from Xilinx User Guide.I've added some names on interface. Are they correct ? And can i have my user interface in figure1(which i wrote as figure2) implement the state diagram of figure 2 ?

[yenigal]

Hi

The attachment is not viewable,can you attach a bigger one showing what you are referring to.

Also refer UG586 for the user interface and timing diagrams to drive data to the MIG.

[dare_bandom]

I've attached them again.Yes,I've refered to UG586 pdf,but i still have some doubts(asked above)

[vsrunga]

Hi,

You need to look into app_* signals descriptions, rest of the things will be taken care by the controller.

For write/read command app_rdy should be high, for write data app_wdf_rdy should be high, to  receive read check app_rddata_valid status

Please refer U586 Command path, write path and read path timing diagrams for better undersatnding

Also I would suggest to generate example design of the core, simulate it  and analyze the signals so that you will have a better picture

Hope this helps

-Vanitha

[dare_bandom]

@vsrunga 

yes,based on MIG ip core, i did generate example traffic generator that xilinx provides.

In many of xilinx user guides like Satish mentions there are waveforms showing app_* signals.How do i see them ?
When i synthesized the top module of example traffic gen & saw the generated waveforms,i can't see those signals

[vsrunga]

Hi,

I am not sure how can you view the genarted waveforms in synthesized design,can you elaborate your flow?

Please simulate example design and load mig_7series_0_mig.v file(ppropriate top level module) so that you can see the signals

[dare_bandom]

@vsrunga 

how can you view the genarted waveforms in synthesized design - my mistake

My Flow :
1) After generating MIG design from Xilinx vivado IP Catalog;to compile the example design i opened IP Example Design(by right clicking on mig_7series_0.xci).
2) Based on the IP Example design,Xilinx creates another IP Example project with example_top as the top module of the new project.
3) In the new example project, i ran behavioral simulation to get data flow analysis & i got the following simulation output(figure-3).

In figure-3,i cannot see the app_* signals (app_cmd,app_addr,app_en etc...).Do i require a user interface module(like a AXI slave-interface module) to get simulation outputs with app_* signals like figure-4 ?

I think figure_3 is simulation o/p of example_top wrapper file of MIG,while figure-4 is simulation o/p of user-interface module ?Am i correct ?

[vsrunga]

Hi,

UI will exist by default.

You need to run the simulation till you see init_calib_complete goes high(60 to 70 us simulation time) .

By default simu;ation will load only example_top.v siganls which does not have UI siganls, so load mig_7series_0_mig.v file signals to waveform then you will be able to see the UI signals

If you can analyze the the hierarchy of example design you will know which modules drives what

Hope this helps

-Vanitha

[dare_bandom]

@vsrunga 

Hi,

You need to run the simulation till you see init_calib_complete goes high(60 to 70 us simulation time) .

In the simulation that i ran(snapshot attched) the init_calib_complete signal remains X(unknown).It isn't going high.Does this mean my memory interface is not ready to be used ?

By default simu;ation will load only example_top.v siganls which does not have UI siganls, so load mig_7series_0_mig.v file signals to waveform then you will be able to see the UI signals

Yes,earlier i did not load these files.Now i added files in mig_7series_0 folder(mig_7series_0.v;mig_7series_0_mig.v;ui,phy;ip_top;ecc;controller;clocking) and still i do not see these UI signals.

[dare_bandom]

@vsrunga 

Hi,

In the above reply i've forgot to set mig_7series_ui_top in simulation directory as the top module.So, I was not seeing those UI(app_*)signals.Now I've change it but they are in high impedance(Z)state. How can i drive them ?

PS: attached in simulation snapshot.

[vsrunga]

Hi,

Please run the simulation for longer time until init_calib_complete is asserted user interface will not be ready.

[yenigal]

Hi

The simulation top file should be still the test bench file(sim_tb_top),you just need to add the signals from the ui_top to the wave window as shown in below snapshot to see the app signals in wave window

[dare_bandom]

@vsrunga ,@yenigal 

Hi,

I added ui signals to wave window.Below is a snapshot.

1) init_calib_complete stays at '0' level after 5 us.How can i assert it to high (PHY does it/i can do it )?Ran the simulation close to 100 us.

2) in UI app_addr[ADDR_WIDTH – 1:0],app_cmd(2:0),etc.. are inputs.How can i assign values to them ?from ui_top i am unable to do it ?

Thanks for your replies despite my persistent asking.

[yenigal]

Hi

Have you modified the example design files or simulating as is?

I see a pulse on the init_calib_complete from your simulation snapshot and it will not deassert once it is asserted unless there are issue's with the clock or reset to the core in simulation.

[dare_bandom]

Hi,

Have you modified the example design files or simulating as is?

simulating the files as it is.

I see a pulse on the init_calib_complete from your simulation snapshot.

u mean the spike(around 45 us) ? or the change in its level from 'X'(unknown) to '0' level at around 2-3 us

[yenigal]

Hi

I mean the spike at 45us.

Can you attach the xci file of Mig to check this at my end.

[dare_bandom]

attached is the .xci file

[dare_bandom]

Hi,

1)   I increased my simulation time from the usual 100 us to 300 us.And now i notice after 105 us,data is getting driven  into   app_wdf_data & also getting read at app_rd_data.(1st snapshot).

2)   Does this usually take this much time ? Or is there any anomaly over here ? init_calib_complete is getting aserted around 5-10 us only,so memory controller is ready.

3)   Also the data getting written & read is different,i'll analyze the waveforms(generated data pattern) more & inform u back.

4) Also when i set simulation for 300 us in simulation settings,it ran for 150 us & stops.No warning/buffer overflow/error message.I checked in message window it shows analysis for 300 us complete ?

[vsrunga]

It is normal that simulation takes long time based on your sysem and IP configuration

If you see the message "test passed" then simulation is ssuccesfful

If you d onot see it please upload your transcript here,  aslo  is error signal low?

[dare_bandom]

Hi,

1) If by error signal, you mean "tg_compare_error";yes,it is low.

2) How can we change/assign app_addr,app_wdf_data etc... For signals like DATA_PATTERN,CMD_PATTERN i see assignments like dgen_all,dgen_hammer etc... But how do i change these signals.

[yenigal]

Hi

Yes if tg_compare_error is low then no errors occured with MIG using the traffic generator during write and read.

You can find description on changing the data and command patterns of traffic generator in UG586

[dare_bandom]

Hi,

1)I know how to change data & command patterns(to hammer,walking1,walking 0 etc...).I wanted to know how to change ui signals like app_addr,app_wdf_data.

By default app_wdf_data gets address as its data.How to change these ?

I tried changing DATA_PATTERN & CMD_PATTERN but this has no effect on app_* signals.

2) Yes,it seems so that there is no error in the design,but somehow the simulation stops after 155 us.But this isn't an issue,because when it stops at 155 us,i run it for additional time( us ) from xsim window.

I've attached a snapshot of my console window.

[dare_bandom]

@yenigal ,@vsrunga 

Hi,

Now if i want to write my data to DDR3 using UI,do i need to write another module(user defined traffic generator) or can i do it with the example design.

Example design is giving me only some data patterns