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Registered: ‎01-09-2013

XHwIcap_SetClbBits on Virtex-5

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I'm trying to use the XHwIcap_SetClbBits-function, but can't seem to get it working.

I can succesfully run the "xhwicap_lut.c" example for the setClb function provided by Xilinx. This example writes the configuration of a single LUT and then reads it back to check if the write was succesful.

However, when I connect this LUT to the PLB bus so that I can test the output of the reconfigured LUT, it appears that it is not the correct LUT that is reconfigured by the setClb function. The output of the LUT does not change when the LUT is reconfigured. I already checked that the coordinates of the LUT match (SLICE_X1Y1:LUTA) using the XDL file.


I know about previous problems in the coordinate calculation functions (, but these seem to be fixed in the driver version I am using.


What is especially weird is that I have tried to systematically read back all LUTs of the FPGA using XHwIcap_GetClbBits and that none of the LUTs match the initial configuration of my test LUT that was set in VHDL, even though I get the correct output when I test this LUT via the PLB.


Is this a known problem? Am I using a wrong driver version?
All suggestions are welcome, because I'm out of ideas. Let me know if you need more information.


Kind regards



Board ML507, Virtex 5

Xilinx EDK v13.4

HWicap v5.01.a, driver v6.00.a

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Registered: ‎01-09-2013

Additional findings:

I believe it has been pointed out before, but it is still the case for version 6.00.a of the HWICAP driver: the content of XHI_CLB_LUT.CONTENTS is the same for SLICE_L and SLICE_M. This makes it impossible to make a distinction between the two slices of a CLB when using the setClb function.

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