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Newbie murph
Newbie
9,738 Views
Registered: ‎07-15-2009

XUPV5-LX110T proper IODELAY settings for DDR2?

Hello,

I'm trying to update a project that used a ML505 board (with the LX50T) so I can use it on the XUPV5-LX110T. I'm building it with the ISE.

 

In the .ucf file, I have these lines (actually, they might even be from a ML509 setup, since i was trying different things):

 

INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl.0.u" LOC = "IDELAYCTRL_X0Y1"; INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl.1.u" LOC = "IDELAYCTRL_X0Y2"; INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl.2.u" LOC = "IDELAYCTRL_X0Y6"; INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl[0].u" LOC = "IDELAYCTRL_X0Y1"; INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl[1].u" LOC = "IDELAYCTRL_X0Y2"; INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl[2].u" LOC = "IDELAYCTRL_X0Y6";

 

When i try to build it I get errors (like this, but many similar):

 

 

ERROR:Place:872 - Delay element "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/ddgen[39].del_dq0" has been placed at IODELAY_X0Y118 due to the following location constraint on component "ddr_dq(39)": COMP "ddr_dq(39)" LOCATE = SITE "V24" LEVEL 1 However, the delay controller that calibrates this delay element has not been used. Please instantiate a delay controller and apply appropriate location constraint, or instantiate one delay controller for the design with out any location constraint. Please refer to the usage document to use the controller efficiently.

 I've searched around, but I cannot find proper values for this board. Does anyone have them, or know where I could get them? I'm useing ISE Foundation 11.1 (webpack didn't support the board target so i switched to foundation). 

 

Thanks,

--Murph 

 

 


 

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8 Replies
Newbie murph
Newbie
9,734 Views
Registered: ‎07-15-2009

Re: XUPV5-LX110T proper IODELAY settings for DDR2?

Additionally, a lot of stuff i have found vaugly related has suggested using tools that either don't work for me or I don't have related project files for. I was just editing the .ucf file by hand to go from ML505-LX50T to XUPV5-LX110T (they're very, very similar). I'm more than willing to set some things up if there's a good way, however.

 

Basically, i'm trying to setup a Leon3 processor (with modifications, but nothing relevant).

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Advisor evgenis1
Advisor
9,694 Views
Registered: ‎12-03-2007

Re: XUPV5-LX110T proper IODELAY settings for DDR2?

There are certain rules on how to use IDELAYCTRL primitive. It's in Xilinx UG190, "IDELAYCTRL Usage and Design Guidelines" section.

 

 

 OutputLogic

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Newbie murph
Newbie
9,654 Views
Registered: ‎07-15-2009

Re: XUPV5-LX110T proper IODELAY settings for DDR2?

That guide tells me "Xilinx strongly recommends using IDELAYCTRL with a LOC constraint." and it tells me "Each IDELAYCTRL module has XY location coordinates" (and how to specify them). However, I see nothing on choosing those location cooridinates. Where would I look for that information?
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Visitor johnfuhrer
Visitor
9,429 Views
Registered: ‎06-05-2009

Re: XUPV5-LX110T proper IODELAY settings for DDR2?

Hi, if you're trying to create a DDR2 memory interface i followed this procedure:

 

1) Open EDK and create a new project including a MPMC (Multi-Port Memory Controller) in your EDK design. Let the wizard choose the pinout.

2) Follow the standalone MIG procedure as described in the MPMC datasheet at pag 68, MIG/MPMC Tool Flow. This will generate an UCF file with

your constraints.

3) Now modify that UCF file replacing the pin LOC constraints with the ones your board uses. If you have designed a custom board the pins must have been chosen using MIG in the first place.

4) Open your MIG design with coregen and do a verify UCF and then an update design. This should read your new pin locations and modify the other constraints accordingly.

5) Use the modified UCF in your project and all should be fine.

 

NOTE: At least in my case MIG update crashes when using version 11.2 of Xilinx tools. I had to use version 10.1 to get it working.

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Observer mmcshmi11
Observer
8,688 Views
Registered: ‎12-13-2009

Re: XUPV5-LX110T proper IODELAY settings for DDR2?

I have been struggling with this same exact problem for a while now. johnfuhrer, I tried the steps you have, but was still unsuccessful. Do you have any more tips for working this?

 

I replaced the constraints, verified and updated the project, and that still gave errors. I found out that there a few more things to change, like adding a "_0" to different parts of the UCF file so it would finally compile without errors. http://www.xilinx.com/support/answers/30899.htm

 

It compiles, but comes up with something like 63 errors and most of those say, "However, the delay controller that calibrates this delay element has not been used. Please instantiate a delay controller and apply appropriate location constraint, or instantiate one delay controller for the design with out any location constraint. Please refer to the usage document to use the controller efficiently."

 

I found somewhere it could be the number of Idelayctrl. My project initially had 3 in the following locations:

# PARAMETER C_NUM_IDELAYCTRL = 3

# PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y5-IDELAYCTRL_X0Y1-IDELAYCTRL_X0Y0

 

but this site (http://www.xilinx.com/support/answers/30309.htm) says for the ML505 board (which is what I thought the xupv5-lx110t is) you should have this line instead:

 PARAMETER C_NUM_IDELAYCTRL = 2

 PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y3-IDELAYCTRL_X1Y4 

 

Does somebody know how to instantiate the delay controller??

 

Thank you! 

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Moderator
Moderator
8,685 Views
Registered: ‎07-30-2007

Re: XUPV5-LX110T proper IODELAY settings for DDR2?

There is an answer record that explains how to find the proper idelayctrl locations

 

http://www.xilinx.com/support/answers/24704.htm




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Observer mmcshmi11
Observer
8,680 Views
Registered: ‎12-13-2009

Re: XUPV5-LX110T proper IODELAY settings for DDR2?

Well changing PARAMETER C_NUM_IDELAYCTRL to 1 and then commenting out the LOC constraint got rid of those errors and eventually gave me a bit file, hope it works :)

 

Thanks for the help though! 

Message Edited by mmcshmi11 on 01-05-2010 11:17 PM
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Visitor shubhamearly
Visitor
6,722 Views
Registered: ‎05-12-2011

Re: XUPV5-LX110T proper IODELAY settings for DDR2?

 


@mmcshmi11 wrote:

Well changing PARAMETER C_NUM_IDELAYCTRL to 1 and then commenting out the LOC constraint got rid of those errors and eventually gave me a bit file, hope it works :)

 

Thanks for the help though! 

Message Edited by mmcshmi11 on 01-05-2010 11:17 PM

Hey  friends,

 

 

Could you please help me in resolving where to make the above changes ? I mean I am also using the LEON3 design as you were. Which file should I add the info [as given by you]: Is it the .ucf file or somewhere else ? I am a beginnner and I really don't know about the back-end design with FPGA .

 

 

Thanks in advance

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