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Contributor
Contributor
9,303 Views
Registered: ‎04-16-2008

XUPV5: "Some of the logic associated with this structure is locked" ??

Hi,

 

I was synthesizing the design of a webserver implemented on XUPV5 board and I got the message below. Would anyone help me out to solve this problem...

 

Thanks in advance,

Salma

 

-------------------- 

 

ERROR:Place:713 - IOB component "fpga_0_DDR2_SDRAM_DDR2_DQ<13>" and IODELAY
   component
   "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/g
   en_dq[13].u_iob_dq/u_idelay_dq" must be placed adjacent to each other into
   the same I/O tile in order to route net
   "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/g
   en_dq[13].u_iob_dq/dq_in". The following issue has been detected:
   Some of the logic associated with this structure is locked. This should cause
   the rest of the logic to be locked.A problem was found at site IODELAY_X0Y56
   where we must place IODELAY
   DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/ge
   n_dq[13].u_iob_dq/u_idelay_dq in order to satisfy the relative placement
   requirements of this logic.  IODELAY
   DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/ge
   n_dqs[0].u_iob_dqs/u_iodelay_dq_ce appears to already be placed there which
   makes this design unplaceable.  
Phase 1.1 (Checksum:13274ea2) REAL time: 42 secs

REAL time consumed by placer: 42 secs
CPU  time consumed by placer: 40 secs
ERROR:Pack:1654 - The timing-driven packing phase encountered an error.

Mapping completed.
See MAP report file "system_map.mrp" for details.
Problem encountered during the packing phase.

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Professor
Professor
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Registered: ‎08-14-2007

This sort of error usually occurs when the SDRAM core was prepared for a different device.

If your MPMC core was prepared for multiple pin-compatible devices be sure you are using

the correct .ucf file for the device on your board.

 

HTH,

Gabor

-- Gabor
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Contributor
Contributor
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Registered: ‎04-16-2008

Hi,

 

Thanks for your reply. I'm using a design originally developed for ML505 board on ML509 board (XUPV5). I've changed the version of the board in the project options in EDK, and I've read that I also need to change the UCF if the FPGA is mentioned in it or if I'm using RocketIO GTPs.

 

You're saying that this is a SDRAM problem and that I need to modify the UCF file. But how do I know what to change in the UCF for it to be correct? 

 

Thanks in advance,

Salma

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Contributor
Contributor
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Registered: ‎06-12-2008

Hi,

 

the MPMC uses the MIG to interface with the DDR2 memory. What I would do is to find a reference design for the ML509 using DDR2 memory, and compare the UCF files, and also the toplevel sdram HDL file. There is a generic there ( I can't remember its name or exact purpose) which has something to do with the placement of IOBs for the memory controller. It is a long string of 0's and 1's. This string needs to correspond with the LOC constraints in your UCF. Normally this is done by the wizard setting up your system and can be quite hard to do manually.

 

So the best thing to do is to find reference design OR make a new XPS project for ML509 with MPMC DDR2 and look at those constraints and HDL files.

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Contributor
Contributor
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Registered: ‎04-16-2008

Hello,

 

Thanks for your answer. I've tried to generate a UCF file by the MIG and put it instead of my UCF because I've read that the UCF generated by the MIG is the correct file that should be tested against. But the same error is still there!

 

Do you have an idea about this parameter that I should change to make sure the IOBs of the memory controller are placed correctly?

 

Thanks in advance,

Salma 

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Professor
Professor
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Registered: ‎08-14-2007

I've seen occasions where ISE will use information from old UCF files even after they are deleted

from the project.  Check your error message against the LOC constraints in the new UCF file

from MIG.  If they don't match you probably need to run "cleanup project files" and start a new build.

 

HTH,

Gabor

-- Gabor
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Contributor
Contributor
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Registered: ‎04-16-2008

Hello,

 

Thanks for your reply.

 

I've cleaned the project and resynthesized but it gave me the same exact error. I'll try what's mentioned here in the last part of this post http://forums.xilinx.com/xlnx/board/message?board.id=Virtex&thread.id=3973

What do yout think?

 

ERROR:Place:713 - IOB component "fpga_0_DDR2_SDRAM_DDR2_DQ<13>" and IODELAY
   component
   "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/g
   en_dq[13].u_iob_dq/u_idelay_dq" must be placed adjacent to each other into
   the same I/O tile in order to route net
   "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/g
   en_dq[13].u_iob_dq/dq_in". The following issue has been detected:
   Some of the logic associated with this structure is locked. This should cause
   the rest of the logic to be locked.A problem was found at site IODELAY_X0Y56
   where we must place IODELAY
   DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/ge
   n_dq[13].u_iob_dq/u_idelay_dq in order to satisfy the relative placement
   requirements of this logic.  IODELAY
   DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/ge
   n_dqs[0].u_iob_dqs/u_iodelay_dq_ce appears to already be placed there which
   makes this design unplaceable. 
Phase 1.1 (Checksum:af1b9de) REAL time: 30 secs

REAL time consumed by placer: 31 secs
CPU  time consumed by placer: 29 secs
ERROR:Pack:1654 - The timing-driven packing phase encountered an error.

Mapping completed.
See MAP report file "system_map.mrp" for details.
Problem encountered during the packing phase.

Design Summary
--------------
Number of errors   :   2
Number of warnings :  67
ERROR:Xflow - Program map returned error code 2. Aborting flow execution...
make: *** [__xps/system_routed] Error 1
Done!

 

 

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Contributor
Contributor
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Registered: ‎06-12-2008

Salma,

 

if you are using a ML509 board then you should be able to create a XPS project/design (with MPMC) in seconds by using the Base System Builder. You get this option when you choose new project in XPS. Select Xilinx as board vendor and hopefully you can select the ML509 board. Otherwise you might need to update your software packages. Have you tried it?

 

If you can generate such a design and synthesize/implement it (and preferably also test it in HW) then you know you have the right setup.

 

Since you are using XPS flow (I assume you are), then forget about that toplevel HDL file I was talking about, because I believe that all hardware related settings are sourced from your MHS file. (Pinout and constraints are still in the UCF). So compare section for MPMC in MHS file of working design vs. your design. A good text editor with diff feature will make it a lot easier.

 

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Contributor
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Registered: ‎04-16-2008

Hello,

 

Thanks for your reply.

 

The whole problem was that the board file of the XUPV5 wasn't available before so it wasn't in the drop down menu of the boards in BSB. So that's why I went through all of this headache! But I guess it's partly solved now. I found the board file of the XUPV5 and I've used it and was able to generate a working project in XPS, which only prints to the HyperTerminal.

I'm trying to make the ethernet project work, but it gave me an error in timing closure and didn't generate the bit file. So, I unchecked the option of "treat the timing closure as an error" and downloaded the design but when I try to ping any web address in the windows command prompt, nothing happens! Shouldn't it show like the webpage of google or so! I'm using the Wireshark network analysis tool, which keeps on showing me the sent/received packets. I'm not quite sure how to test all of this. It's my first time to do such a project :(

Message Edited by salmabakr on 11-11-2009 01:20 AM
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Contributor
Contributor
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Registered: ‎06-12-2008

So the DDR2 memory is working now?

 

Timing errors related to the ethernet is another issue. So is your problems with the webserver. If you want to make sense of what you see with wireshark you need to familiarize yourself with TCP/IP and HTTP protocols.

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Contributor
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Registered: ‎04-16-2008

No, the DDR isn't working! But if the design worked partly without it then I don't need it for this one. Only for further designs that require it.

I've had a similar problem with the DDR in the XUPV2 board. It wasn't working either. I got a modified board file online that should have made it work, but it wasn't successful.

I guess there's something wrong with me then! :) 

 

I've tried the instructions given here http://www.xilinx.com/univ/xupv5-lx110t/design_files/MIG/XUPV5-LX110T_MIG_Design_Creation.pdf

But in vain!

 

I've also tried to verify the UCF and update it in MIG. It gave me an error message but no logs for it.

 

It's really messy when dealing with DDR...

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Observer
Observer
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Registered: ‎12-13-2009

So, I've also been trying to interface the DDR2 to the XUPV5-LX110T board without luck. 

 

I started with the Base System Builder in EDK 10.1 to add an MPMC IP core for the DDR2. It came up with the same exact error that began this thread. This didn't work because the BSB doesn't have the LX110T chip and that has to be changed after the project is made.

 

So, I opened CORE generator and started a new design with the Memory Interface Generator (MIG v2.3). MIG 2.3 has the LX110T design built in so I thought the UCF file it generated would be correct, but those constraints didn't match what was given for the board. Another person the forums here said that if you change those constraints in the MIG generated UCF that you could re-verify the design and it would generate the full, appropriate, UCF file for this board with the DDR2.

 

Has anybody made any more progress that I with this board and the DDR2? 

 

Thanks 

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