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Xilinx Employee
Xilinx Employee
9,366 Views
Registered: ‎03-09-2011

Xilinx® Training on Virtex Series FPGAs

Play Video Virtex-6 Memory Resources
Learn how to fully utilize the Virtex®-6 distributed memory, block memory, and FIFO resources, use the Memory Interface Generator (MIG) to build a custom memory controller for your off-chip memory component.

Updated: Sept 2012
Play Video Virtex-6 Slice and I/O Resources
Learn how to describe the basic slice and I/O resources available in Virtex-6 FPGAs.

Updated: Sept 2012
Play Video Virtex-6 Clocking Resources
Learn how to detail the clocking resources available in the Virtex-6 FPGA, specify the resources available in the Clock Management Tile (CMT), describe the basics of the PLL capabilities.

Updated: Sept 2012
Play Video Virtex-6 & Spartan-6 FPGA HDL Coding Techniques
Learn how to code your register resources so your design will have fewer control sets and run at a higher system speed, avoid the most common coding mistakes that reduce device utilization and system speed, anticipate how your design will map to the register resources, code your design so you can infer more of the dedicated hardware resources, avoid the most common coding mistakes which hurt device utilization, reduce your dependence on global resets by taking advantage of the Global Set/Reset net (GSR).

Updated: Sept 2012
Play Video Virtex-5 FPGA HDL Coding Techniques
Learn how to code properly for Virtex-5 FPGA register resources. You will also know how to manage your control signal usage so that you can build a smaller FPGA design that will run at the highest system speed possiblel, code properly for 6-input LUT and block RAM resources in the Virtex-5 FPGA. You will also know how to manage your control signal usage so that you can build a high-speed FPGA design. Finally, you will identify the most important considerations for migrating an existing design to the Virtex-5 FPGA.

Updated: Sept 2012
Designing with the 7-Series FPGA Families - Updated September 2012

Are you interested in learning how to effectively utilize 7 series architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Essentials of FPGA Design course. This course focuses on understanding as well as how to properly design for the primary resources found in this popular device family. - Test Your Knowledge


Designing with the Spartan-6 and Virtex-6 FPGA Families - Updated March 2011

Are you interested in learning how to effectively utilize Spartan-6 FPGA or Virtex-6 FPGA architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Essentials of FPGA Design course. This course focuses on understanding as well as how to properly design for the primary resources found in these popular device families. - Test Your Knowledge


Designing with the Virtex-5 FPGA Family - Updated June 2009

Interested in learning how to effectively utilize Virtex-5 FPGA architectural resources? Targeted towards experienced Xilinx users who have already completed Essentials of FPGA Design and Designing for Performance, this course focuses on understanding as well as designing into several of the new and enhanced resources found in our newest device. - Test Your Knowledge


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