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Visitor
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Registered: ‎03-10-2010

a question of V5 rocketio

I have two PCB boards with an XC5VSX95T on each board, and four MGTs’s TX of fpga1  is connected with four MGTs’s RX of fpga2,so I have eight GTPs to channel bonding.  Now the fpga1’s GTPs are designed to use a txoutclkout to drive eight txusrclk_in,I use chipscope to test tile_txdata_i is true and eight lanes are aligned,but in fpga2 I test eight tile_rxdata_i  are not aligned ,because I have no more DCM to use,so I use a rxrecclkout to drive eight rxusrclk_in. I want to know how to align the eight lines?Must every lane be drived by itself's rxrecclk?

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-03-2008

Re: a question of V5 rocketio

  1. If you are connecting 4 MGTs Transmitters to 4 MGTs Receivers than this is 4 lanes, not 8.
  2. When you channel bond all of the transmitters must use the same REFCLK, TXUSRCLK, and TXUSRCLK2
    1. A single DCM and 1 or 2 BUFGs (depends on TX data width) would be used to drive all of the TXUSRCLK and TXUSRCLK2 inputs as was as the TX data source.
  3. When you channel bond all of the receivers must use the same REFCLK, RXUSRCLK and RXUSRCLK2
    1. A single DCM and 1 or 2 BUFGs (depends on RX data width) would be used to drive all of the RXUSRCLK and RXUSRCLK2 inputs as well as the RX data sink.
    2. If you are using 8B10B encoding and clock correction then you should not use RXRECCLK and instead use either the TXOUTCLK or REFCLKOUT from one of the MGTs 
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Visitor
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Registered: ‎03-10-2010

Re: a question of V5 rocketio

1. sorry,i connected four transceivers ,so I have 8 lanes.
2. i use a single txoutclk to drive a single DCM ,then to drive 8 txusrclk and txusrclk2.
3. my MGT receives are not on the same PCB board of MGT transmitters,and they have no
shared clock,so i use the MGTCLK to drive the refclkin.if not use rxrecclk,are RXDATAs correct?
4. i test the rxchanbondseq signal is zero, why  channels not bonding? whether i insert some idle codes to channel synchronous?
thank!
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Xilinx Employee
Xilinx Employee
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Registered: ‎01-03-2008

Re: a question of V5 rocketio

It is fine for a channel-bonded link to go between boards.  The MGTs on both boards need to have a REFCLK source and the frequency of these two clocks must be within 100ppm.

 

If the channel-bonded protocol used 8b10b encoding, clock correction then there is no need to use RXRECCLK.

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Visitor
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Registered: ‎03-10-2010

Re: a question of V5 rocketio

this is my  fpga program,fpga1 and fpga2 are not on the same pcb board,and poweron sequence is random, i use chipscope to find : six channels are bonding mostly ,but occasionally  one or two channels are not bonding.so this situation is random,i know why?
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