06-04-2014 08:11 AM
In the design , I use"slave selectmap"mode, a 10M signal drive three VIRTEX FPGA CCLK configure signals.We measure cclk waveform using TEK DPO73304 oscilloscope and find that there is a knee point on the rising edge ,about 150mV heigh and 1ns width at about 1.3V .I want to know if there is structure like"schmitt trigger" in the design of cclk in VIRTEX FPGA that can help erase the influence of "knee point" in rising edge of cclk signal. Or, what is the limit requirement about signal integrity of cclk? thanks very much.
06-04-2014 01:05 PM
Xilinx parts unfortunately have no hysteresis on their configuration and JTAG inputs. You'll need to clean up the clock to prevent issues. The Configuration user guide recommends termination of the CCLK signal at the FPGA. It's not clear from your post whether your board routes the signal as a star, which would permit this sort of temination, or as a daisy-chain, which would not. Ideally any clock source that drives multiple loads should have individual buffers per load.
Another point is that 1.3V is likely to be in a threshold region, and even with no apparent overshoot, it's possible that any additional noise could cause extra edges to be detected by the part. The actual logic threshold depends on the voltage used by the CCLK pin. All config inputs are LVCMOS referenced to the associated bank voltage.
Finally you talk about Virtex, but there are many different families of Virtex, and some may be more sensitive to high-frequency noise on the clock inputs than others. Virtex 7 I/O is much faster than very old Virtex, Virtex E, Virtex II, etc.
06-05-2014 06:15 AM
I used virexII series FPGA in my old design.In the datasheet of VIRTEX II , LVTTL input has hysteresis function ,about 100mV hyystersis.So I wonder if fpga cclk pin would accept this waveform and could run correctly. The board had been manufactured ,cclk signal had been routed as daisy chain and terminated with "source seried resistance(24 ohm)". The board worked well so far, but I doubt that the product can work well in the lifetime.plz ,thx.
06-05-2014 08:41 AM
Using source series termination will always create the sort of plateau in the signal that you have observed. However this is more likely to work OK on Virtex II than on newer parts. One possible suggestion to help with signal integrity is to reduce the value of the source series resistor. This will increase the level where the plateau occurs. If you can make the plateau happen above the input threshold region, then you should have little or no chance of extra clocks due to noise. You will see some overshoot due to the mismatched impedance, but hopefully there should be a reasonable balance point where the selected source resistance is high enough to prevent excessive overshoot and / or ringing, while still keeping the plateau above the threshold level. If not, you may need to change the circuit to use parallel termination at the end of the run instead of the source series termination.
06-06-2014 07:07 AM
thx very much , and I still think that configuration and jtag pin of virtex-II has hysteresis function, about 100mV, according to the datasheet(page 53 Table6 on DS031).is it right?