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Observer fatima06
Observer
11,403 Views
Registered: ‎11-03-2011

big delay between CLKIN and CLKO of DCM in LX50T Virtex-5

Hi all,

 I'm using a DMC to generate clock for my flip-flops inside an LX50T Virtex-5. I have a big delay between CLKIN and CLKO that the Feddback delay element inside the DCM is incapable to ajust. The max skew (delay) between the two clocks (CLKIN and CLKO) equals 260 ps for this device while my delay is eqal to 2.5 ns. Which clock will be send to my flip-flops if the feeback element is unable to ajust this delay???

 

Thank you

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5 Replies
Historian
Historian
11,393 Views
Registered: ‎02-25-2008

Re: big delay between CLKIN and CLKO of DCM in LX50T Virtex-5


@fatima06 wrote:

Hi all,

 I'm using a DMC to generate clock for my flip-flops inside an LX50T Virtex-5. I have a big delay between CLKIN and CLKO that the Feddback delay element inside the DCM is incapable to ajust. The max skew (delay) between the two clocks (CLKIN and CLKO) equals 260 ps for this device while my delay is eqal to 2.5 ns. Which clock will be send to my flip-flops if the feeback element is unable to ajust this delay???


Why is the delay so large?

----------------------------Yes, I do this for a living.
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Observer fatima06
Observer
11,390 Views
Registered: ‎11-03-2011

Re: big delay between CLKIN and CLKO of DCM in LX50T Virtex-5

The delay is so large (2.5 ns) because it exceeds the max value of the delay supported by the DCM (260 ps) !!!!
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Historian
Historian
11,380 Views
Registered: ‎01-23-2009

Re: big delay between CLKIN and CLKO of DCM in LX50T Virtex-5

I am not sure where you are getting this 260ps number - but you are clearly misinterpreting something (or explaning what you need incorrectly). The whole point of the DCM is to adjust the phase of the CLK0 output so that the CLKIN and CLKFB are in phase - effectively the DCM will cancel out all the delay placed between the CLK0 and the CLKFB. This delay is usually the delay of the BUFG and clock network, but can be any delay, including a delay outside the FPGA and back it. It can definitely accommodate delays larger than 260ps or 2.5ns or even bigger.

 

So, what exactly are you trying to do, and what are you expecting the DCM to do - somewhere along the way, something is being misinterpreted.

 

Avrum

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Observer fatima06
Observer
11,365 Views
Registered: ‎11-03-2011

Re: big delay between CLKIN and CLKO of DCM in LX50T Virtex-5

HI,

Thank you Avrum for your answer. I try to study a situation where I have a DCM inside my FPGA that provide the clock for all my registers. I imagine that I have a fault that affects my clock source and this delay is equal to 2.5 ns. So if the clock source is affected by the delay, automatiquely CLKIN is also affected but what will happend to the clock provided to all the registers of my FPGA? Does the DCM able to mask this delay ? and which clock arrive to my clock network?

 

Thank you

 

Fatima,

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Moderator
Moderator
11,323 Views
Registered: ‎02-16-2010

Re: big delay between CLKIN and CLKO of DCM in LX50T Virtex-5

Check ug190 for this,
If CLKIN is stopped for 100 ms or longer, the DCM powers down.

More details from the user guide.

the clock should not be stopped for more than 100 ms to minimize the
effect of device cooling; otherwise, the tap delays might change. The clock should be
stopped during a Low or a High phase, and must be restored with the same input clock
period/frequency. During this time, LOCKED stays High and remains High when the
clock is restored. Thus, a High on LOCKED does not necessarily mean that a valid clock is
available.
When stopping the input clock (CLKIN remains High or Low for one or more clock cycles),
one to nine more output clock cycles are still generated as the delay line is flushed. When
the output clock stops, the CLKIN stopped (DO[1]) signal is asserted. When the clock is
restarted, the output clock cycles are not generated for one to eight clocks while the delay
line is filled. The most common case is two or three clocks. The DO[1] signal is deasserted
once the output clock is generated. CLKIN can be restarted with any phase relationship to
the previous clock. If the frequency has changed, the DCM requires a reset. The DO[1] is
forced Low whenever LOCKED is Low. When the DCM is in the locking process, DO[1]
status is held Low until LOCKED is achieved.
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