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Visitor
Visitor
2,224 Views
Registered: ‎07-20-2010

clocking problem

Hello.

 

I have a design with differential clock connected to clock capable pins on the Virtex5 FPGA. The clock comes from an external clock and data recovery chip. In my design I deserialize data using this recovered clock and then pass the data to a local clock domain. But there seems to be a problem with the recovered clock in the design - if I drive a simple counter with this clock it doesn't increment on each clock cycle as it shoould but rather increments "randomly" (sometimes staying the same for a couple of thousand clock cycles).

 

I am using the same design on a another board with Spartan6 FPGA and it works perfectly there. The only difference is that on the Spartan6 board the clock is connected to a GCLK pin and I use the IBUFGDS input buffer to convert the differential clock to a single ended clock and then a BUFG buffer. On Virtex5 board I cannot use the IBUFGDS buffer, because the clock is connected to a clock capable pin instead of a GCLK pin, so I use IBUFDS -> BUFIO -> BUFR -> BUFG and it doesn't work.

 

Any help on how to address this problem will be highly appreciated, thank you.

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Moderator
Moderator
2,165 Views
Registered: ‎07-30-2007

There doesn't seem to be a need for the BUFIO and probably not for the BUFG either.  Try to use IBUFDS -> BUFR.  The BUFR should have enough "reach" to accomplish the counting.  What is the frequency of the clock.

 

-R




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