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Explorer
Explorer
14,789 Views
Registered: ‎02-04-2011

delay line design in virtex4

Dear friends,

                        I am trying to design a delay line in XC4VLX200 FPGA. I knwo that it has IDELAY but no ODELAY. Can any one suggest how to design a delay line in FPGA.

 

Any help is appreciated.

thanks

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16 Replies
Explorer
Explorer
14,753 Views
Registered: ‎02-04-2011

Re: delay line design in virtex4

any inputs plz.
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Historian
Historian
14,743 Views
Registered: ‎02-25-2008

Re: delay line design in virtex4


@waris.mohammad wrote:

Dear friends,

                        I am trying to design a delay line in XC4VLX200 FPGA. I knwo that it has IDELAY but no ODELAY. Can any one suggest how to design a delay line in FPGA.

 

Any help is appreciated.

thanks


How about providing more details?

What is the maximum delay time? What is the delay granularity (minimum delay time)? Are you delaying single bits or multi-bit words?

----------------------------Yes, I do this for a living.
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Explorer
Explorer
14,733 Views
Registered: ‎02-04-2011

Re: delay line design in virtex4

I have 40MHz clock signal that i want  to  delay  in steps of 400 ps.i need 64 taps.

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Explorer
Explorer
14,732 Views
Registered: ‎02-04-2011

Re: delay line design in virtex4

and i want to generate many outputs with different phases .
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Historian
Historian
14,725 Views
Registered: ‎02-25-2008

Re: delay line design in virtex4


@waris.mohammad wrote:

I have 40MHz clock signal that i want  to  delay  in steps of 400 ps.i need 64 taps.


In an FPGA? Pretty much impossible.

----------------------------Yes, I do this for a living.
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Teacher muzaffer
Teacher
14,721 Views
Registered: ‎03-31-2012

Re: delay line design in virtex4

want to generate many outputs with different phases .

 

As you are not likely to get this in a Xilinx FGPA, if you tell us why you think you need this maybe we can tell you another way to solve your problem.

 

Also let me guess, at some point, you will want to select of these 64 clocks to register some flops?

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Explorer
Explorer
14,704 Views
Registered: ‎02-04-2011

Re: delay line design in virtex4

so how much is achievable in v4 fpga?

i want to generate clocks for ccds.design need to support 3 different types of ccds.so i thought i will use delay lines.

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Moderator
Moderator
14,692 Views
Registered: ‎02-16-2010

Re: delay line design in virtex4

check using the DCM_TAP functionality available. Refer to Virtex-4 FPGA user guide for more details.
http://www.xilinx.com/support/documentation/user_guides/ug070.pdf

Specification about TAP delay can be found in the data sheet Table 50
http://www.xilinx.com/support/documentation/data_sheets/ds302.pdf
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Historian
Historian
14,688 Views
Registered: ‎02-25-2008

Re: delay line design in virtex4


@waris.mohammad wrote:

so how much is achievable in v4 fpga?

i want to generate clocks for ccds.design need to support 3 different types of ccds.so i thought i will use delay lines.


What CCD needs clocks with that sort of timing resolution?

----------------------------Yes, I do this for a living.
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Explorer
Explorer
12,957 Views
Registered: ‎02-04-2011

Re: delay line design in virtex4

design  need to support more than 1 ccd.

one examples are ft18 from dalsa.the reset gate pulse is critical.

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Explorer
Explorer
12,957 Views
Registered: ‎02-04-2011

Re: delay line design in virtex4

dear venkata,

i need to generate many clock .

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Teacher muzaffer
Teacher
12,956 Views
Registered: ‎03-31-2012

Re: delay line design in virtex4

I think your design approach may need revision. Take a look at this app note which is doing the FT18 interface. Are you trying to accomplish the same goal?
http://pdf.datasheetarchive.com/indexerfiles/Datasheet-038/DSA0061336.pdf
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Historian
Historian
12,952 Views
Registered: ‎02-25-2008

Re: delay line design in virtex4


@waris.mohammad wrote:

design  need to support more than 1 ccd.

one examples are ft18 from dalsa.the reset gate pulse is critical.


Generally, the design is done to support a specific CCD. If you need to support a different sensor, you modify the design as necessary. It's a fool's errand to think that you could possibly support multiple devices in the manner you're considering.

 

It's not like you're going to just swap out sensors in the camera without changing other aspects of their operation, such as clock voltage levels and biases and such.

----------------------------Yes, I do this for a living.
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Explorer
Explorer
12,927 Views
Registered: ‎02-27-2008

Re: delay line design in virtex4

You may want to consider using an application-specifc IC for this task.  For example, the AD9970 (and relatives) allow you to run a CCD at 40 MHz and choose the horizontal clock rising and falling edges from 64 PLL taps, exactly as you describe.

 

-Greg

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Teacher muzaffer
Teacher
12,917 Views
Registered: ‎03-31-2012

Re: delay line design in virtex4

It seems you don't need to generate many clocks but the ability to shift your edge precisely. I think you can use an IDELAY element to do the latter.
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Explorer
Explorer
12,824 Views
Registered: ‎02-04-2011

Re: delay line design in virtex4

We need Odelay for the same. Which is not available in V4 FPGA.

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