09-17-2015 09:41 PM
Hi
i had been working on a cutomized board of Virtex 5
among many other one input is LVDS . previously i had been terminating it in the FPGA using DIFF_TERM=TRUE in ucf
but now the bord is modified by placing termination resistance on board
i have removed the above command from ucf
but the program is not working properly but if i remove the module running on LVDS input the rest of the program starts working what could be probably wrong or what should be done to resolvethe issue
best regrds
uzmeed
09-17-2015 10:21 PM
09-17-2015 10:50 PM
Virtex-5 FPGA User Guide ( ver5.4, 13334 KB ) [PDF]
The Virtex®-5 FPGA User Guide includes chapters on clocking resources, clock management technology, phase-locked loops, block RAM, Configurable Logic Blocks (CLBs), SelectIO™ resources, and SelectIO logic resources. |
09-17-2015 11:26 PM
Hi aher
I mean to say that program is behaving not exactly the same as it used to before the modifications
to me the modification are of very small like the clocjk pin shifter from local to global clock pin
and the termination of LVDS which we used to do by ucf is done by placing the resistors on PCB
still the behaviour is not same
regards
uzmeed
09-17-2015 11:34 PM - edited 09-17-2015 11:34 PM
@uzmeed Can you give a try with below constraint in ucf?
DIFF_TERM=FALSE
09-17-2015 11:36 PM
HI
I will try it again but i did it
it dint work