differential in virtex 5

uzmeed · ‎09-17-2015

Hi

i had been working on a cutomized board of Virtex 5

among many other one input is LVDS . previously i had been terminating it in the FPGA using DIFF_TERM=TRUE in ucf

but now the bord is modified by placing termination resistance on board

i have removed the above command from ucf

but the program is not working properly but if i remove the module running on LVDS input the rest of the program starts working what could be probably wrong or what should be done to resolvethe issue

best regrds

uzmeed

aher · ‎09-17-2015

Hi,

What do you mean by "the program is not working properly"? are you facing issue on hardware board or on software? and what issue are you facing?

Thanks,
Shreyas

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balkris · ‎09-17-2015

Virtex-5 FPGA User Guide ( ver5.4, 13334 KB ) [PDF]

The Virtex®-5 FPGA User Guide includes chapters on clocking resources, clock management technology, phase-locked loops, block RAM, Configurable Logic Blocks (CLBs), SelectIO™ resources, and SelectIO logic resources.

Design File(s)

ug190_SSO_Calculator.zip

Thanks and Regards
Balkrishan
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uzmeed · ‎09-17-2015

Hi aher

I mean to say that program is behaving not exactly the same as it used to before the modifications

to me the modification are of very small like the clocjk pin shifter from local to global clock pin

and the termination of LVDS which we used to do by ucf is done by placing the resistors on PCB

still the behaviour is not same

regards

uzmeed

pratham · ‎09-17-2015

@uzmeed Can you give a try with below constraint in ucf?

DIFF_TERM=FALSE

-Pratham

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uzmeed · ‎09-17-2015

HI

I will try it again but i did it

it dint work