you can either instantiate or infer BRAMs, following the code examples in the xilinx library guide for Virtex II.
(You also find examples in the Template menu of the ISE IDE.
Or you can use coregen and add BRAMs to your project (which you intantiate as a whole memory block).
Acess is easy. Once you applied the address and have the controll signals set adequately the data is available on the output on the next valid clock edge.
(The latency may change depending on your BRAM Parameters, see the Datasheet for details)
Have a nice synthesis