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Visitor
Visitor
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Registered: ‎08-18-2014

how to create clock in ucf

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Hello all

 

Im new to virtex family, currently working on VC707. Im trying to create a clock of 33Mhz and input it to my design.

 

According to board manual, I spotted these two clocks in master ucf, how can i utilize them to creat the 33Mhz clock? and what does differential clock mean?

 

 

NET         USER_CLOCK_P                LOC = AK34 | IOSTANDARD=LVCMOS18;

 

NET         USER_CLOCK_N                LOC = AL34 | IOSTANDARD=LVCMOS18;

 

 

 

 

 

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Adventurer
Adventurer
24,825 Views
Registered: ‎04-07-2014

Hi Ahmed,

 

  1. Please find the attached .ucf file for vc707.
  2. Use following constraints.

           NET      "CLK_200MHZ_SYSACE_P"       LOC = "E19"   |   IOSTANDARD=LVDS;
           NET      "CLK_200MHZ_SYSACE_N"       LOC = "E18"   |   IOSTANDARD=LVDS; 

 

  • Instantiate an MMCM (to generate 33MHz from this 200MHz differential crystal clk input) with "differential pin capable" inputs and connect  directly to this clk pads.
  • Otherwise use IBUFGDS primitive(differential to single ended clock buffer) to get a single ended clock and divide(by 6d) this clock using a counter logic to get 33MHz as per ur previous post link .
  • However If you put a clock signal on a ordinary net  the signal quality (slew rate etc.) will worsen.

Thanks,

Akshay

 

 

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Visitor
Visitor
15,665 Views
Registered: ‎08-18-2014

will this do? I'll appreciate your help.

 

NET   USER_CLOCK_P      LOC = AK34 |IOSTANDARD=LVCMOS18;

NET       USER_CLOCK_P   TNM_NET = USER_CLOCK_P;

TIMESPEC  TS_USER_CLOCK_P = PERIOD "USER_CLOCK_P" 30.3 ns HIGH 50 %;

 



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Xilinx Employee
Xilinx Employee
15,647 Views
Registered: ‎01-03-2008
Constraints cannot be used to create a clock frequency. The constraints that you wrote set the pin location for your inputs and define a timing constraint that will be used for timing analysis. You need to use the 200 MHz clock input that is available on the VC707 and a MMCM or PLL to divide by 6 to get a 33 MHZ clock for your design.

Note: 33 MHz is generally short hand or 33.33333 MHz or a 30.00ns period.
------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Visitor
Visitor
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Registered: ‎08-18-2014

thank you very much for your reply, but still i dont know how to use the 200Mhz clock input available on the VC707 (i dont see it in the master ucf!!). Im familiar already with clock division so that i can change it my required frequency.

 

In SP605 i used to write this line to input the 33Mhz clock and inside the code i divide it to get the reqired freq.

NET      "CLK_33MHZ_SYSACE"       LOC = "N19";

 

In the VC707 datasheet there is part about the 200Mhz SYSCLK_P and SYSCLK_N which are connected to pins E19 and E18, but the master ucf doesnt say anything about them!!

 

I'll appreciate it if you can lead me or give me an example so that i can understand how to input the on board 200Mhz clock to my design.

 

 

 

 

 

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Adventurer
Adventurer
24,826 Views
Registered: ‎04-07-2014

Hi Ahmed,

 

  1. Please find the attached .ucf file for vc707.
  2. Use following constraints.

           NET      "CLK_200MHZ_SYSACE_P"       LOC = "E19"   |   IOSTANDARD=LVDS;
           NET      "CLK_200MHZ_SYSACE_N"       LOC = "E18"   |   IOSTANDARD=LVDS; 

 

  • Instantiate an MMCM (to generate 33MHz from this 200MHz differential crystal clk input) with "differential pin capable" inputs and connect  directly to this clk pads.
  • Otherwise use IBUFGDS primitive(differential to single ended clock buffer) to get a single ended clock and divide(by 6d) this clock using a counter logic to get 33MHz as per ur previous post link .
  • However If you put a clock signal on a ordinary net  the signal quality (slew rate etc.) will worsen.

Thanks,

Akshay

 

 

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Xilinx Employee
Xilinx Employee
15,609 Views
Registered: ‎07-31-2012

Hi,


The master UCF should be having these constraints. You can also check Pg 88 of the VC707 guide for this constraints - http://www.xilinx.com/support/documentation/boards_and_kits/vc707/ug885_VC707_Eval_Bd.pdf which are given as below.

 

set_property PACKAGE_PIN E19 [get_ports SYSCLK_P]
set_property IOSTANDARD LVDS [get_ports SYSCLK_P]
set_property PACKAGE_PIN E18 [get_ports SYSCLK_N]
set_property IOSTANDARD LVDS [get_ports SYSCLK_N]

 

instantiating these should help you access the 200MHz input clock.

Thanks,
Anirudh

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Visitor
Visitor
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Registered: ‎08-18-2014

thanks guys for your time and replay, i think im getting in the right direction. I used the IBUFGDS primitive to generate single clock and divided it by 6 and fed it to a UART. The UART gave me wrong result in hyperterminal (uart has another divisor (143d) to generate 115200 baud rate). I also got this warning.

 

WARNING:Pack:1186 - One or more I/O components have conflicting property values.

 

here is my top level design and ucf.

entity clk_top is
port (
	SYSCLK_P : in std_logic;
	SYSCLK_N : in std_logic;
	uart_tx : out std_logic
	);
end clk_top;

architecture Behavioral of clk_top is

component uart_top is
port (
clkn: in std_logic; 
tx: out std_logic
);
end component;


signal CLK: std_logic := '0';
signal clk_i: std_logic := '0';
signal count2: integer := 0; 


begin

process (CLK) is
begin 
if rising_edge(clk) then 
  count2 <= count2+1; 
	if count2 = 6 then 
      clk_i <= clk_i xor '1';
	   count2 <= 0;      
    end if; 
end if; 
end process;


IBUFGDS_inst : IBUFGDS
generic map (
		IOSTANDARD => "LVDS_25")
port map (
		O => CLK,
		I => SYSCLK_P,
		IB => SYSCLK_N
		);

uart_inst: uart_top 
port map (
clkn => clk_i, 
tx => uart_tx
);
		


end Behavioral;

 

NET "SYSCLK_P"   LOC = "E19" | IOSTANDARD=LVDS;
NET "SYSCLK_N"   LOC = "E18" | IOSTANDARD=LVDS;

NET "uart_tx"    LOC = "AU36" | IOSTANDARD=LVCMOS18;

 

 

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Visitor
Visitor
15,597 Views
Registered: ‎08-18-2014

hi Anirudh,

 

So my ucf should be like this?

 

NET "SYSCLK_P"   LOC = "E19" | IOSTANDARD=LVDS;
NET "SYSCLK_N"   LOC = "E18" | IOSTANDARD=LVDS;

set_property PACKAGE_PIN E19 [get_ports SYSCLK_P]
set_property IOSTANDARD LVDS [get_ports SYSCLK_P]
set_property PACKAGE_PIN E18 [get_ports SYSCLK_N]
set_property IOSTANDARD LVDS [get_ports SYSCLK_N]
NET "uart_tx" LOC = "AU36" | IOSTANDARD=LVCMOS18;

 

 

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Adventurer
Adventurer
15,589 Views
Registered: ‎04-07-2014

Hi Ahmed,

 

  1. WARNING:Pack:1186 - One or more I/O components have conflicting property values. Is due to the mismatch in I/O standards used in  IBUFGDS primitive instantiation(LVDS_25) and in the UCF file(LVDS).
  2. The IOSTANDARD for an HR bank is LVDS_25 and the IOSTANDARD for an HP is LVDS.
  3. Since your clk pins are on the HP banks, replace the iostandard attribute LVDS_25 with LVDS in the primitive instatiation.
  4. Please go through the manual for using clocking wizard .http://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v3_3/clk_wiz_gsg521.pdf


Thanks,
Akshay 

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Visitor
Visitor
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Registered: ‎08-18-2014

thanks Akshay for your help, now the UART works but not perfectly (i divided the input 200Mhz clock by 868d), first 3 data bytes sent to hyperterminal are garbage the rest are ok. Is this a side-effect of using IBUFGDS primitive? is it better to use PPL or MMCM to generate clock? 

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