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Newbie frankptalin
Registered: ‎06-03-2011

how to enter fully routed design in Virtex-6 for high unrouted nets design

I found one strange phenomenon in ISE13.1 P&R flow as below,

1. the p&r options had been set to "map -ol high -xe n -pr b" and "par -ol high -xe n",

2. for my two different designs ,

    1) one design (60% slices used)  has about 452961 unrouted nets in phase 3 of PAR stage, it can enter "fully routed design", so it can be routed successfully.

    2) another design(62% slices used) has about 686790 unrouted nets in phase 3 of PAR stage, but it can't enter "fully routed design", just "partially routed design" and routed unsuccessfully.


It seems that if the unrouted nets is larger than some number, ISE will not try to use fully routed deign method for the continue routing, as my design just used 62% slice.


How to solve this problem?


Thanks in advance.


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Advisor eilert
Registered: ‎08-14-2007

Re: how to enter fully routed design in Virtex-6 for high unrouted nets design


please take a look at the numbers you provided.

Your 60% design has about 450k-nets, while your 62%design has about 686k-nets, which is 50% more than in the smaller design.

So it's not the small difference in used logic ressources, but the heavy difference in the wiring.

While everyone is aware of the fact that logic ressources are limited, the same applies to the routing ressources.

But it's not so easy to compute a measure of usage, like what is given for the logic ressources.


Have you checked somehow wether the larger design is routable at all?

Did you succeed with some other ISE version?

Have you tried to use a larger device, just to see wether it works there or not?


Have a nice synthesis


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