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Visitor zhiqi_huawei
Visitor
2,335 Views
Registered: ‎11-21-2011

how to understand the relationship between the configure ram and the fpga funcion?

Now ,aftar the bitstream is be load the configure ram,  then the information about the lut/flii-flop/ram are be configured .

 

but after the whole function is initial ,   I just want to know the configure ram  can affect the funciont  realy tim.

 

for example ,if the configure ram is wrong with some bit , then will the function  of the FPGA  run wrong at once ?

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Scholar austin
Scholar
2,320 Views
Registered: ‎02-27-2008

Re: how to understand the relationship between the configure ram and the fpga funcion?

z,

 

Configuration bits determine function (connections, logic in look up tables, initial conditions of user flip-flops, etc.)

 

If any one bit (or more) is wrong, the CRC is bad, and the device will not configure (INIT goes low, DONE stays low).


If every one of the configuration bits is valid, and the CRC matches, then DONE goes high, and everything is as programmed, and will do whatever you told it to do (results should match your simulations, agree with your test-benches).

 

If after DONE goes high, the device gets upset, from a neutron strike (a soft error event, or soft error upset -- SEU), the function may change.


Bits that are used, are called "essential bits":  they are bits set, or reset, to match your design.  They are about 30% of the bits in the bitstream.


A bit that if flipped (changed) that causes a functional failure to your design is called a "critical bit."  Critical bits are less than 10% of the bitstream (90% of the bits are unused in time, or in space).

 

If you wish to flip bits to find your design's  critical bits, the SEU Monitor IP block allows you to flip bits, and see what happens.  That IP block will also protedct against upsets by finding, and fixing them (after they accur).


If a bit flip can cause a functional failure with a probability of .02 to .10 (2 to 10%), then only one in 50, to one in 10 upsets causes a functional failure.  Running the SEU IP Monitor will extend the mean time between failures by up to 30% in some cases:  the failure may still cause a functional failure, but by fixing it quickly, that bit may not be critical at that instant in time.

 

So, the configuration bits tell the FPGA device what to do.  If they are correct, the CRC is good, and the device begins operation.  If they are bad before configuration is finished, the device does not start (DONE does not go high).  If a bit changes after the device is operational, there is a 2 to 10% chance that bit was critical, and the design will experience a functional failure.

 

(Try inputting the above into google translate -- I find it very helpful!)

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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