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Newbie toadione
Newbie
3,040 Views
Registered: ‎06-18-2011

implement a boundary scan on virtex-4 XC4VSX35

hi,

 

I try to implement a boundary scan on virtex-4 XC4VSX35, but during the implemention design phase i have some error :

 

Release 9.2.04i Map J.40
Xilinx Map Application Log File for Design 'SdrIoring'

Design Information
------------------
Command Line   : C:\Xilinx92i\bin\nt\map.exe -ise
C:/stage/SFF_SDR/examples/default/hard_func_ex/sff_sdr_user_interrupt/fpga/ise/S
FF_SDR_User_Interrupt.ise -intstyle ise -p xc4vsx35-ff668-10 -cm area -pr b -k 4
-c 100 -o SdrIoring_map.ncd SdrIoring.ngd SdrIoring.pcf
Target Device  : xc4vsx35
Target Package : ff668
Target Speed   : -10
Mapper Version : virtex4 -- $Revision: 1.36 $
Mapped Date    : Fri Jun 17 14:56:46 2011

Mapping design into LUTs...
ERROR:MapLib:30 - LOC constraint W32 on TCK is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint Y12 on TDI is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint Y13 on TDO is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint Y11 on TMS is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.

Error found in mapping process, exiting...
Errors found during the mapping phase.  Please see map report file for more
details.  Output files will not be written.

Design Summary
--------------
Number of errors   :   4
Number of warnings :   2

 

 

I already check the package that i'm using and is the right one.

maybe it's because there are no Slice X/Y location for TD0 TDI TCK and TMS for this pin ( http://www.xilinx.com/support/packagefiles/v4packages/4vsx35ff668.txt line 12,14,15,18).

 

i put the same location pin in my vhdl file :

 

  attribute loc : string;
 
  --JTAG pin locations
  attribute loc of TCK                                : signal is "W32";
  attribute loc of TDO                                : signal is "Y13";
  attribute loc of TMS                                : signal is "Y11";
  attribute loc of TDI                                  : signal is "Y12";
  --end JTAG pin locattion

 

if someone can help me. thank you

 

 

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1 Reply
Scholar drjohnsmith
Scholar
3,031 Views
Registered: ‎07-09-2009

Re: implement a boundary scan on virtex-4 XC4VSX35

Hi

 

possible to0 simple an answer.

 

the JTAG pins are fixed on the device,

    you do not need to do anything in the vhdl or the ucf file.

 

JTAG is always included in the FPGA.

 

 

 

 

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