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Observer lino89
Observer
9,557 Views
Registered: ‎09-22-2013

iodelay1

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how i can give reset signal(RST) to the block 

it is in variable mode

clock signal is 100mhz

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Xilinx Employee
Xilinx Employee
16,319 Views
Registered: ‎02-06-2013

Re: iodelay1

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Hi

 

The RST signal is an active-High reset and is synchronous to the input clock signal (C) which you can drive to the idelay instantiation.

 

You can refer the language templetes or the doc below for more details.

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_4/virtex6_hdl.pdf

Regards,

Satish

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Observer lino89
Observer
9,555 Views
Registered: ‎09-22-2013

Re: iodelay1

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1.jpg
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Observer lino89
Observer
9,554 Views
Registered: ‎09-22-2013

Re: iodelay1

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i need output from data out
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Xilinx Employee
Xilinx Employee
16,320 Views
Registered: ‎02-06-2013

Re: iodelay1

Jump to solution

Hi

 

The RST signal is an active-High reset and is synchronous to the input clock signal (C) which you can drive to the idelay instantiation.

 

You can refer the language templetes or the doc below for more details.

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_4/virtex6_hdl.pdf

Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------

View solution in original post

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