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Registered: ‎01-23-2013

lead forming

I wanted  to know  the Xilinx standard recommendations for lead
forming of the below FPGA

MIL Part no:5962-9957201QYC
Xilinx Part No: XQV300-4CB228Q


Thanks in advance

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Xilinx Employee
Xilinx Employee
Registered: ‎07-31-2012

Re: lead forming



Check Pg 31 of this link - link


However if you need further info please contact the FAE in your region for such information. YOu can find the Xilinx contacts from the link - link


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Registered: ‎02-16-2010

Re: lead forming

I am not sure if I completely understood about lead forming.

I find this information in ug112. Please check if it helps.

The orientation of the die in the package and the orientation of the package on the PC
board affect the PC board layout. PLCC and PQFP packages specify pins in a
counterclockwise direction, when viewed from the top of the package (the surface with the
Xilinx logo). PLCCs have pin 1 in the center of the beveled edge while all other packages
have pin 1 in one corner, with one exception: The 100-pin and 165-pin CQFPs (CB100 and
CB164) for the XC3000 devices have pin 1 in the center of one edge.
CQFP packages specify pins in a clockwise direction, when viewed from the top of the
package. The user can make the pins run counterclockwise by forming the leads such that
the logo mounts against the PC board. However, heat flow to the surrounding air is
impaired if the logo is mounted down.

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