11-09-2011 01:25 AM - edited 11-09-2011 01:26 AM
First of all: I’m using the Xilinx ML605 Board with FasterTechnology FM-S18 daughterboard.
My design looks like follows:
What I’ve got is a time multiplex of some datastreams on one GTX Receiver. Because it is a multiplex signal, it’s not possible to do a clock correction (the clock correction sequences of each single datastream will never be at the same time, I’m sure). So I tried to recover a clock out of the multiplex signal. Using this clock on the one GTX Receiver with the multiplex signal (rxrecclock connected to MMCM and then supplying rxusrclk and rxusrclk2) works fine (txusrslk and txusrclk2 are supplied by txoutclk of the same GTX, the refclks are different but both from the FM-S18 and in allowed banks). I tried to use the recovered clock to drive txusrclk and txusrclk2 of the transmitters of the demultiplexed datastreams but that causes errors (displayed by Spirent Testcenter).
The logic of the multiplexer and demultiplexer works fine as long as I use the same clock for all transmitters and receivers. So the error must be addicted to the clocking. The different clocks have to work somehow because in real life you also won’t have multiplexer and demultiplexer working with the same clock because they are at different places.
Could someone please help me a little bit?
Thanks in advance!
11-09-2011 08:07 AM
> with FasterTechnology FM-S18 daughterboard
This is a 8 port SFP/SFP+ FMC module
> Because it is a multiplex signal, it’s not possible to do a clock correction (the clock correction
> sequences of each single datastream will never be at the same time, I’m sure).
What is creating the input multiplexed data stream and how is it doing it?
What control do you have over the protocol of this data stream?