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Anonymous
Not applicable
9,293 Views

sata validatation on ML605

Hi

 

I am doing FPGA validation on ML605 with virtex 6 gtx transceiver.

 

After OOB and speed negotiations, when actual transfers started, we are seeing disparity and decode errors on rx lines.

But received data's CRC is corrected.

 

Are we getting these errors because of RX Equlazation settings?

 

if so kindly post me the RX and TX setting for virtex 6 gtx phy.

 

Thanking you

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Community Manager
Community Manager
9,273 Views
Registered: ‎07-23-2012

Hi,

Which version of GT core are you using?
If it is v1.6 or earlier, please refer to http://www.xilinx.com/support/answers/35653.htm

In general, data errors attributes to poor channel. I would recommend you to first test the quality of your channel using IBERT and make sure that you achieve a good BER.

Are you targeting SATA gen 1/2/3?
Please note that Gen3 in not officially supported i.e. we don't have the characterized attributes/parameter values of GTX for SATA gen3 protocol.

Regards,
Krishna
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Moderator
Moderator
9,269 Views
Registered: ‎02-16-2010

when you find disparity errors and notintable errors, can you try asserting GTRXRESET and check?
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