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lalobegar
Adventurer
Adventurer
10,936 Views
Registered: ‎02-13-2013

tapped delay line

Hi, 

 

I'm trying to implement a tapped delay line as shown in the attached image. I use the carry4 blocks of the FPGA to generate the tapped delay line, here is my code...

 

entity tdl is
  generic(
     n_carry: positive:=64
       );
  port(start,clk,reset,stop: in std_logic;
                                      led: out std_logic_vector(4*n_carry-1 downto 0)
                                              );
end tdl;

 

architecture Behavioral of tdl is

            signal reg_delay : std_logic_vector(4*n_carry-1 downto 0);

  begin

           gcarry: for i in 0 to n_carry-1 generate
               g_firstcarry: if i=0 generate
                        cmp_carry:CARRY4 port map(
                              CO => reg_delay(3 downto 0),
                              CI => '0',
                              CYINIT => start,
                               DI => "0000",
                              S => "1111"
                       );
                    end generate;
                  gnextcarry: if i>0 generate
                          cmp_carry:CARRY4 port map(
                             CO => reg_delay(4*(i+1)-1 downto 4*i),
                             CI =>(reg_delay(4*i-1)),
                             CYINIT => '0',
                             DI => "0000",
                             S => "1111"
                                        );
                            end generate;
                     end generate;

                     process(stop,reg_delay)
                         begin
                               if stop='1' then
                                   led<=reg_delay;
                             end if;
                       end process;

end Behavioral;

 

 

I think the problem is in the process, because I have the delay line, but I cannot move the data to another register (led).

 

Can anybody help me with this?

 

Regards.

tapped delay line.PNG
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2 Replies
avrumw
Expert
Expert
10,925 Views
Registered: ‎01-23-2009

There is a whole bunch of things here...

 

First, I think you are confused with what the output of the carry chain is. The carry chain is pure combinatorial, so the bus named "reg_delay" is the output of the "delay chain" - thus effectively the D inputs to the Flip-flops shown below. So, I would call this "carry_out", not "reg_delay"

 

Second, the "STOP" sampling is supposed to be the clock of your FFs - again, your naming is odd - lets say that the output of the flops is the "reg_delay" (not the input, as above).. To do this, you need to actually code for a flip-flop. I don't do VHDL, but its something like this

 

                   process(stop)
                         begin
                               if rising_edge(stop) then
                                   reg_delay <=carry_out;
                             end if;
                       end process;

 

Now lets deal with the bigger issues. How are you planning to distributed "STOP" to the flip-flops? In an FPGA you have two choices, local routing or a clock network. If you use local routing, the skew of the distribution to the flip-flops will be large and uncontrolled - far larger than the propagation delay through the carry chain. If you plan to use a clock buffer (assuming STOP is in a clock capable input pin), then the insertion delay is measured in nanoseconds; so the delay from whatever pin you are using for STOP to the clock inputs of the FFs is large. I am pretty sure both of these are unacceptable for your application.

 

Next, for this to work, you need to ensure that the path from the START input pin to the input of the carry chain and the path from the STOP input pin to the clock pins of all flops is identical. There is no way to do this in an FPGA; the path from the START input to the carry chain can be constrained to be "no more than X", but can't be constrained to "no less than y". Again, this is probably unacceptable for what you are trying to do.

 

Finally, the carry chain in most modern FPGAs is a fast carry lookahead of 4 bits. There is no guarnatee that the delay from CYINIT to the 4 output bits CI is monotonic or in equal delays - they are likely actually to be the same delay to all 4 outputs. Furthermore, the delay from CO of one 4 bit carry unit to the CI of the next is larger than the delay inside the carry unit. Once again - this won't do what you need it to do...

 

All in all, you probably need to realize that this is basically impossible in an FPGA...

 

Avrum

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lalobegar
Adventurer
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10,920 Views
Registered: ‎02-13-2013

Hi, you are right, the name of my variables are odd, I also dont know why I wrote "stop". Although the image says "stop" actually is the main clock. 

 

The main purpose is to realize a TDC, and there are various works about this. They have used the carry4 to implement the tapped delay line, thats the reason I'm trying to do that, because I know somebody already did.

 

Now, I know that the delay for each bit is not the same, but somebody advise me to use look up tables (I do not know how to use them yet).

 

The code you wrote is exactly what I should write. I just want to latch the FF with the rising edge of the CLK to get a thermometer code...

 

 

thermometer code.PNG
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