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Observer lino89
Observer
11,498 Views
Registered: ‎09-22-2013

virtex 6 iodelay1

i need iodelay1 block in my design but from simulation my delay between ny datain and dataout are not as expected.

its showing without the delay of my cnt value.

 

pls help me to resolve this problem.

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8 Replies
Xilinx Employee
Xilinx Employee
11,493 Views
Registered: ‎04-16-2012

Re: virtex 6 iodelay1

Hi,

Are you running behavioral simulation?
If yes, try running post route simulation (timing simulation).

Thanks
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Observer lino89
Observer
11,486 Views
Registered: ‎09-22-2013

Re: virtex 6 iodelay1

i am not familiar with that simulation

how to do that.

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Xilinx Employee
Xilinx Employee
11,481 Views
Registered: ‎04-16-2012

Re: virtex 6 iodelay1

Hi,

 

Steps to follow:

 

1. Implement the design.

2. double click on post place and route simulation model (Snapshot below)

post_par.PNG

3. Then switch to simulation (snapshot below)

par.PNG

4. Then double click on "simulate Post-Place & route simulation"

smulat.PNG

 

Thanks

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Observer lino89
Observer
11,476 Views
Registered: ‎09-22-2013

Re: virtex 6 iodelay1

IT IS ASKING FOR IDELAYCTRL IS THIS CONNECTION RIGHT

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Observer lino89
Observer
11,454 Views
Registered: ‎09-22-2013

Re: virtex 6 iodelay1

done it still has the same problem

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Community Manager
Community Manager
11,440 Views
Registered: ‎07-23-2012

Re: virtex 6 iodelay1

Can you share the testcase to reproduce the issue?
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Observer lino89
Observer
11,432 Views
Registered: ‎09-22-2013

Re: virtex 6 iodelay1

the delay is not based on tap value

i need var_loadable mode of iodelay

from the datasheet they have given that the delay is based on the cntvalue we give to the iodelay1 block

i also didn't understand to use idelayctrl

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Moderator
Moderator
11,383 Views
Registered: ‎02-16-2010

Re: virtex 6 iodelay1

I think you should connect the invert of the RDY output from IDELAYCTRL to RST input of IODELAYE1. This will ensure to make IODELAY operate only after IDELAYCTRL is ready.

Please note that idelayctrl must be reset if RDY output goes LOW because of the absence of REFCLK at later point.
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