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Visitor ino1988
Visitor
10,512 Views
Registered: ‎09-10-2013

virtex5 gtp for sata2

Hi, i'm using virtex5 gtp to run sata2 as sata host communicating with sata pm. Sometimes when the data sent by the gtp, the pm does not have any response. So, using a v5-gtx to replace the sata pm, i get the following results.

1. the data(0xB5B5B5B5) get in the gtx is contrary to the data(0x4A4A4A4A) sent by gtp , and no errors from the gtp and gtx.
2. no valid data received by the gtx, 8b10b decoder disparity errors from the gtx.
3. good data.

 

The 3 results may appear in the different times  in  a same project.


I run AURORA between the gtp and gtx, and it's ok.  The sata device(pm) carried by the GTX is ok in the other project.

I guess the problem may be caused by the attribute configuration of the gtp.

Is here anyone can give some help or ideas. Thanks.

 

 



The GTP configuration :

GTP_DUAL #
     (
      //_______________________ Simulation-Only Attributes __________________                                                                          

      .SIM_GTPRESET_SPEEDUP        (SIM_GTPRESET_SPEEDUP),
      .SIM_PLL_PERDIV2             (SIM_PLL_PERDIV2),

      //___________________________ Shared Attributes _______________________                                                                          

      //---------------------- Tile and PLL Attributes ----------------------                                                                          

      .CLK25_DIVIDER                  (6),
      .CLKINDC_B                        ("TRUE"),
      .OOB_CLK_DIVIDER              (6),
      .OVERSAMPLE_MODE             ("FALSE"),
      .PLL_DIVSEL_FB                   (2),
      .PLL_DIVSEL_REF                 (1),
      .PLL_TXDIVSEL_COMM_OUT       (1),// 1), //2 for GEN1 and 1 for GEN2                                                                              
      .TX_SYNC_FILTERB                (1),

      //______________________ Transmit Interface Attributes ________________                                                                          

      //----------------- TX Buffering and Phase Alignment ------------------                                                                          

      .TX_BUFFER_USE_0            ("TRUE"),
      .TX_XCLK_SEL_0              ("TXOUT"),
      .TXRX_INVERT_0              (5'b00000),

      .TX_BUFFER_USE_1            ("TRUE"),
      .TX_XCLK_SEL_1              ("TXOUT"),
      .TXRX_INVERT_1              (5'b00000),

      //------------------- TX Serial Line Rate settings --------------------                                                                          

      .PLL_TXDIVSEL_OUT_0         (1),//1 ),//2),//2 for GEN1 and 1 for GEN2                                                                           

      .PLL_TXDIVSEL_OUT_1         (1),//1),//2),                                                                                                       

      //------------------- TX Driver and OOB signalling --------------------                                                                          

      .TX_DIFF_BOOST_0           ("TRUE"),

      .TX_DIFF_BOOST_1           ("TRUE"),

      //---------------- TX Pipe Control for PCI Express/SATA ---------------                                                                          

      .COM_BURST_VAL_0            (4'b1010),

      .COM_BURST_VAL_1            (4'b1010),

      //_______________________ Receive Interface Attributes ________________                                                                          

      //---------- RX Driver,OOB signalling,Coupling and Eq.,CDR ------------                                                                          

      .AC_CAP_DIS_0               ("FALSE"),
      .OOBDETECT_THRESHOLD_0      (3'b111),
      .PMA_CDR_SCAN_0             (27'h6c08040),
      .PMA_RX_CFG_0               (25'h0dce111),
      //.PMA_RX_CFG_0               (25'h09f0089),                                                                                                     
      .RCV_TERM_GND_0             ("FALSE"),
      .RCV_TERM_MID_0             ("TRUE"),
      .RCV_TERM_VTTRX_0           ("TRUE"),
      .TERMINATION_IMP_0          (50),

      .AC_CAP_DIS_1               ("FALSE"),
      .OOBDETECT_THRESHOLD_1      (3'b111),
      .PMA_CDR_SCAN_1             (27'h6c08040),
      .PMA_RX_CFG_1               (25'h0dce111),
      //.PMA_RX_CFG_1               (25'h09f0089),                                                                                                     
      .RCV_TERM_GND_1             ("FALSE"),
      .RCV_TERM_MID_1             ("TRUE"),
      .RCV_TERM_VTTRX_1           ("TRUE"),
      .TERMINATION_IMP_1          (50),

      .TERMINATION_CTRL           (5'b10100),
      .TERMINATION_OVRD           ("FALSE"),

      //------------------- RX Serial Line Rate Settings --------------------                                                                          

      .PLL_RXDIVSEL_OUT_0         (1),//2),//2 for GEN1 and 1 for GEN2                                                                                 
      .PLL_SATA_0                 ("FALSE"),

      .PLL_RXDIVSEL_OUT_1         (1),
      .PLL_SATA_1                 ("FALSE"),


      //------------------------- PRBS Detection ----------------------------                                                                          

      .PRBS_ERR_THRESHOLD_0       (32'h00000008),

      .PRBS_ERR_THRESHOLD_1       (32'h00000008),

      //------------------------- PRBS Detection ----------------------------                                                                          

      .PRBS_ERR_THRESHOLD_0       (32'h00000008),

      .PRBS_ERR_THRESHOLD_1       (32'h00000008),

      //------------------- Comma Detection and Alignment -------------------                                                                          

      .ALIGN_COMMA_WORD_0         (2),
      .COMMA_10B_ENABLE_0         (10'b1111111111),
      .COMMA_DOUBLE_0             ("FALSE"),
      .DEC_MCOMMA_DETECT_0        ("TRUE"),
      .DEC_PCOMMA_DETECT_0        ("TRUE"),
      .DEC_VALID_COMMA_ONLY_0     ("FALSE"),
      .MCOMMA_10B_VALUE_0         (10'b1010000011),
      .MCOMMA_DETECT_0            ("TRUE"),
      .PCOMMA_10B_VALUE_0         (10'b0101111100),
      .PCOMMA_DETECT_0            ("TRUE"),
      .RX_SLIDE_MODE_0            ("PCS"),

      .ALIGN_COMMA_WORD_1         (2),
      .COMMA_10B_ENABLE_1         (10'b1111111111),
      .COMMA_DOUBLE_1             ("FALSE"),
      .DEC_MCOMMA_DETECT_1        ("TRUE"),
      .DEC_PCOMMA_DETECT_1        ("TRUE"),
      .DEC_VALID_COMMA_ONLY_1     ("FALSE"),
      .MCOMMA_10B_VALUE_1         (10'b1010000011),
      .MCOMMA_DETECT_1            ("TRUE"),
      .PCOMMA_10B_VALUE_1         (10'b0101111100),
      .PCOMMA_DETECT_1            ("TRUE"),
      .RX_SLIDE_MODE_1            ("PCS"),

      //------------------- RX Loss-of-sync State Machine -------------------                                                                          

      .RX_LOSS_OF_SYNC_FSM_0      ("FALSE"),
      .RX_LOS_INVALID_INCR_0      (8),
      .RX_LOS_THRESHOLD_0         (128),

      .RX_LOSS_OF_SYNC_FSM_1      ("FALSE"),
      .RX_LOS_INVALID_INCR_1      (8),
      .RX_LOS_THRESHOLD_1         (128),

      //------------ RX Elastic Buffer and Phase alignment ports ------------                                                                          

      .RX_BUFFER_USE_0            ("TRUE"),
      .RX_XCLK_SEL_0              ("RXREC"),

      .RX_BUFFER_USE_1            ("TRUE"),
      .RX_XCLK_SEL_1              ("RXREC"),

      //--------------------- Clock Correction Attributes -------------------                                                                          

      .CLK_CORRECT_USE_0          ("TRUE"),
      .CLK_COR_ADJ_LEN_0          (4),
      .CLK_COR_DET_LEN_0          (4),
      .CLK_COR_INSERT_IDLE_FLAG_0 ("FALSE"),
      .CLK_COR_KEEP_IDLE_0        ("FALSE"),
      .CLK_COR_MAX_LAT_0          (18),
      .CLK_COR_MIN_LAT_0          (16),
      .CLK_COR_PRECEDENCE_0       ("TRUE"),
      .CLK_COR_REPEAT_WAIT_0      (0),
      .CLK_COR_SEQ_1_1_0          (10'b0110111100),
      .CLK_COR_SEQ_1_2_0          (10'b0001001010),
      .CLK_COR_SEQ_1_3_0          (10'b0001001010),
      .CLK_COR_SEQ_1_4_0          (10'b0001111011),
      .CLK_COR_SEQ_1_ENABLE_0     (4'b1111),
      .CLK_COR_SEQ_2_1_0          (10'b0000000000),
      .CLK_COR_SEQ_2_2_0          (10'b0000000000),
      .CLK_COR_SEQ_2_3_0          (10'b0000000000),
      .CLK_COR_SEQ_2_4_0          (10'b0000000000),
      .CLK_COR_SEQ_2_ENABLE_0     (4'b0000),
      .CLK_COR_SEQ_2_USE_0        ("FALSE"),
      .RX_DECODE_SEQ_MATCH_0      ("TRUE"),

      .CLK_CORRECT_USE_1          ("TRUE"),
      .CLK_COR_ADJ_LEN_1          (4),
      .CLK_COR_DET_LEN_1          (4),
      .CLK_COR_INSERT_IDLE_FLAG_1 ("FALSE"),
      .CLK_COR_KEEP_IDLE_1        ("FALSE"),
      .CLK_COR_MAX_LAT_1          (18),
      .CLK_COR_MIN_LAT_1          (16),
      .CLK_COR_PRECEDENCE_1       ("TRUE"),
      .CLK_COR_REPEAT_WAIT_1      (0),
      .CLK_COR_SEQ_1_1_1          (10'b0110111100),
      .CLK_COR_SEQ_1_2_1          (10'b0001001010),
      .CLK_COR_SEQ_1_3_1          (10'b0001001010),
      .CLK_COR_SEQ_1_4_1          (10'b0001111011),
      .CLK_COR_SEQ_1_ENABLE_1     (4'b1111),
      .CLK_COR_SEQ_2_1_1          (10'b0000000000),
      .CLK_COR_SEQ_2_2_1          (10'b0000000000),
      .CLK_COR_SEQ_2_3_1          (10'b0000000000),
      .CLK_COR_SEQ_2_4_1          (10'b0000000000),
      .CLK_COR_SEQ_2_ENABLE_1     (4'b0000),
      .CLK_COR_SEQ_2_USE_1        ("FALSE"),
      .RX_DECODE_SEQ_MATCH_1      ("TRUE"),

      //-------------------- Channel Bonding Attributes ---------------------                                                                          

      .CHAN_BOND_1_MAX_SKEW_0     (7),
      .CHAN_BOND_2_MAX_SKEW_0     (7),
      .CHAN_BOND_LEVEL_0          (CHAN_BOND_LEVEL_0),
      .CHAN_BOND_MODE_0           (CHAN_BOND_MODE_0),
      .CHAN_BOND_SEQ_1_1_0        (10'b0000000000),
      .CHAN_BOND_SEQ_1_2_0        (10'b0000000000),
      .CHAN_BOND_SEQ_1_3_0        (10'b0000000000),
      .CHAN_BOND_SEQ_1_4_0        (10'b0000000000),
      .CHAN_BOND_SEQ_1_ENABLE_0   (4'b0000),
      .CHAN_BOND_SEQ_2_1_0        (10'b0000000000),
      .CHAN_BOND_SEQ_2_2_0        (10'b0000000000),
      .CHAN_BOND_SEQ_2_3_0        (10'b0000000000),
      .CHAN_BOND_SEQ_2_4_0        (10'b0000000000),
      .CHAN_BOND_SEQ_2_ENABLE_0   (4'b0000),
      .CHAN_BOND_SEQ_2_USE_0      ("FALSE"),
      .CHAN_BOND_SEQ_LEN_0        (1),
      .PCI_EXPRESS_MODE_0         ("FALSE"),

      .CHAN_BOND_1_MAX_SKEW_1     (7),
      .CHAN_BOND_2_MAX_SKEW_1     (7),
      .CHAN_BOND_LEVEL_1          (CHAN_BOND_LEVEL_1),
      .CHAN_BOND_MODE_1           (CHAN_BOND_MODE_1),
      .CHAN_BOND_SEQ_1_1_1        (10'b0000000000),
      .CHAN_BOND_SEQ_1_2_1        (10'b0000000000),
      .CHAN_BOND_SEQ_1_3_1        (10'b0000000000),
      .CHAN_BOND_SEQ_1_4_1        (10'b0000000000),
      .CHAN_BOND_SEQ_1_ENABLE_1   (4'b0000),
      .CHAN_BOND_SEQ_2_1_1        (10'b0000000000),
      .CHAN_BOND_SEQ_2_2_1        (10'b0000000000),
      .CHAN_BOND_SEQ_2_3_1        (10'b0000000000),
      .CHAN_BOND_SEQ_2_4_1        (10'b0000000000),
      .CHAN_BOND_SEQ_2_ENABLE_1   (4'b0000),
      .CHAN_BOND_SEQ_2_USE_1      ("FALSE"),
      .CHAN_BOND_SEQ_LEN_1        (1),
      .PCI_EXPRESS_MODE_1         ("FALSE"),

      //---------------- RX Attributes for PCI Express/SATA ---------------                                                                            

      .RX_STATUS_FMT_0            ("SATA"),
      .SATA_BURST_VAL_0           (3'b100),
      .SATA_IDLE_VAL_0            (3'b100),
      .SATA_MAX_BURST_0           (7),
      .SATA_MAX_INIT_0            (22),
      .SATA_MAX_WAKE_0            (7),
      .SATA_MIN_BURST_0           (4),
      .SATA_MIN_INIT_0            (12),
      .SATA_MIN_WAKE_0            (4),
      .TRANS_TIME_FROM_P2_0       (16'h003c),
      .TRANS_TIME_NON_P2_0        (16'h0019),
      .TRANS_TIME_TO_P2_0         (16'h0064),

      .RX_STATUS_FMT_1            ("SATA"),
      .SATA_BURST_VAL_1           (3'b100),
      .SATA_IDLE_VAL_1            (3'b100),
      .SATA_MAX_BURST_1           (7),
      .SATA_MAX_INIT_1            (22),
      .SATA_MAX_WAKE_1            (7),
      .SATA_MIN_BURST_1           (4),
      .SATA_MIN_INIT_1            (12),
      .SATA_MIN_WAKE_1            (4),
      .TRANS_TIME_FROM_P2_1       (16'h003c),
      .TRANS_TIME_NON_P2_1        (16'h0019),
      .TRANS_TIME_TO_P2_1         (16'h0064)
      )
   GTP_DUAL_HOST_PHY
     (

      //---------------------- Loopback and Powerdown Ports ----------------------                                                                     
      .LOOPBACK0                      (3'b000),
      .LOOPBACK1                      (3'b000),
      .RXPOWERDOWN0                   (2'b00),
      .RXPOWERDOWN1                   (2'b00),
      .TXPOWERDOWN0                   (2'b00),
      .TXPOWERDOWN1                   (2'b00),
      //--------------------- Receive Ports - 8b10b Decoder ----------------------                                                                     
      .RXCHARISCOMMA0                 ({rxchariscomma0_float_i,RXCHARISCOMMA0_OUT}),
      .RXCHARISCOMMA1                 ({rxchariscomma1_float_i,RXCHARISCOMMA1_OUT}),
      .RXCHARISK0                     (rxcharisk0[1:0]),
      .RXCHARISK1                     (rxcharisk1[1:0]),
      .RXDEC8B10BUSE0                 (1'b1),
      .RXDEC8B10BUSE1                 (1'b1),
      .RXDISPERR0                     ({rxdisperr0_float_i,rxdisperr}),
      .RXDISPERR1                     ({rxdisperr1_float_i,RXDISPERR1_OUT}),
      .RXNOTINTABLE0                  ({rxnotintable0_float_i,RXNOTINTABLE0_OUT}),
      .RXNOTINTABLE1                  ({rxnotintable1_float_i,RXNOTINTABLE1_OUT}),
      .RXRUNDISP0                     ({rxrundisp0_float_i,RXRUNDISP0_OUT}),
      .RXRUNDISP1                     ({rxrundisp1_float_i,RXRUNDISP1_OUT}),
      //----------------- Receive Ports - Channel Bonding Ports ------------------                                                                     
      .RXCHANBONDSEQ0                 (RXCHANBONDSEQ0),
      .RXCHANBONDSEQ1                 (),
      .RXCHBONDI0                     (3'b000),
      .RXCHBONDI1                     (3'b000),
      .RXCHBONDO0                     (),
      .RXCHBONDO1                     (),
      .RXENCHANSYNC0                  (1'b1),
      .RXENCHANSYNC1                  (1'b1),
      //----------------- Receive Ports - Clock Correction Ports -----------------                                                                     
      .RXCLKCORCNT0                   (RXCLKCORCNT0),
      .RXCLKCORCNT1                   (),
      //------------- Receive Ports - Comma Detection and Alignment --------------                                                                     
      .RXBYTEISALIGNED0               (RXBYTEISALIGNED0),
      .RXBYTEISALIGNED1               (),
      .RXBYTEREALIGN0                 (RXBYTEREALIGN0),
      .RXBYTEREALIGN1                 (),
      .RXCOMMADET0                    (rxcommadet0),
      .RXCOMMADET1                    (),
      .RXCOMMADETUSE0                 (1'b1),
      .RXCOMMADETUSE1                 (1'b1),
      .RXENMCOMMAALIGN0               (1'b1),
      .RXENMCOMMAALIGN1               (1'b1),
      .RXENPCOMMAALIGN0               (1'b1),
      .RXENPCOMMAALIGN1               (1'b1),
      .RXSLIDE0                       (1'b0),
      .RXSLIDE1                       (1'b0),
      //--------------------- Receive Ports - PRBS Detection ---------------------                                                                     
      .PRBSCNTRESET0                  (1'b0),
      .PRBSCNTRESET1                  (1'b0),
      .RXENPRBSTST0                   (2'b00),
      .RXENPRBSTST1                   (2'b00),
      .RXPRBSERR0                     (),
      .RXPRBSERR1                     (),
      //----------------- Receive Ports - RX Data Path interface -----------------                                                                     
      .RXDATA0                        (rxdata_phy0),
      .RXDATA1                        (rxdata_phy1),
      .RXDATAWIDTH0                   (1'b1),
      .RXDATAWIDTH1                   (1'b1),
      .RXRECCLK0                      (),
      .RXRECCLK1                      (),
      .RXRESET0                       (gtp_reset),//rxreset0), //|phyreset0),                                                                          
      .RXRESET1                       (gtp_reset),//rxreset1), //|phyreset1),                                                                          
      .RXUSRCLK0                      (gtp_rxusrclk),
      .RXUSRCLK1                      (gtp_rxusrclk),
      .RXUSRCLK20                     (gtp_rxusrclk2),
      .RXUSRCLK21                     (gtp_rxusrclk2),
      //----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------                                                                     
      .RXCDRRESET0                    (gtp_reset), //|phyreset0),                                                                                      
      .RXCDRRESET1                    (gtp_reset), //|phyreset1),                                                                                      
      .RXELECIDLE0                    (rxelecidle0),
      .RXELECIDLE1                    (rxelecidle1),
      .RXELECIDLERESET0               (rxelecidlereset0),
      .RXELECIDLERESET1               (rxelecidlereset1),
      .RXENEQB0                       (1'b1),
      .RXENEQB1                       (1'b1),
      .RXEQMIX0                       (2'b00),
      .RXEQMIX1                       (2'b00),
      .RXEQPOLE0                      (4'b0000),
      .RXEQPOLE1                      (4'b0000),
      .RXN0                           (RXN0_IN),
      .RXN1                           (RXN1_IN),
      .RXP0                           (RXP0_IN),
      .RXP1                           (RXP1_IN),
      //------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------                                                                     
      .RXBUFRESET0                    (gtp_reset), //|phyreset0),                                                                                      
      .RXBUFRESET1                    (gtp_reset), //|phyreset1),                                                                                      
      .RXBUFSTATUS0                   (),
      .RXBUFSTATUS1                   (),
      .RXCHANISALIGNED0               (RXCHANISALIGNED0),
      .RXCHANISALIGNED1               (),
      .RXCHANREALIGN0                 (RXCHANREALIGN0),
      .RXCHANREALIGN1                 (),
      .RXPMASETPHASE0                 (1'b0),
      .RXPMASETPHASE1                 (1'b0),
      .RXSTATUS0                      (rxstatus0),
      .RXSTATUS1                      (rxstatus1),
      //------------- Receive Ports - RX Loss-of-sync State Machine --------------                                                                     
      .RXLOSSOFSYNC0                  (RXLOSSOFSYNC0_OUT),
      .RXLOSSOFSYNC1                  (RXLOSSOFSYNC1_OUT),
      //-------------------- Receive Ports - RX Oversampling ---------------------                                                                     
      .RXENSAMPLEALIGN0               (1'b0),
      .RXENSAMPLEALIGN1               (1'b0),
      .RXOVERSAMPLEERR0               (RXOVERSAMPLEERR0),
      .RXOVERSAMPLEERR1               (),
      //------------ Receive Ports - RX Pipe Control for PCI Express -------------                                                                     
      .PHYSTATUS0                     (),
      .PHYSTATUS1                     (),
      .RXVALID0                       (),
      .RXVALID1                       (),
      //--------------- Receive Ports - RX Polarity Control Ports ----------------                                                                     
      .RXPOLARITY0                    (1'b0),
      .RXPOLARITY1                    (1'b0),
      //----------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------                                                                     
      .DADDR                          (7'b0),
      .DCLK                           (1'b0),//gtp_txusrclk2),                                                                                         
      .DEN                            (1'b0),
      .DI                             (16'b0),
      .DO                             (),
      .DRDY                           (),
      .DWE                            (1'b0),
      //------------------- Shared Ports - Tile and PLL Ports --------------------                                                                     
      .CLKIN                          (gtp_refclk),
      .GTPRESET                       (~rst_n),
      .GTPTEST                        (4'b0000),
      .INTDATAWIDTH                   (1'b1),
      .PLLLKDET                       (TILE0_PLLLKDET_OUT),
      .PLLLKDETEN                     (1'b1),
      .PLLPOWERDOWN                   (1'b0),
      .REFCLKOUT                      (gtp_refclkout),
      .REFCLKPWRDNB                   (1'b1),
      .RESETDONE0                     (resetdone0),
      .RESETDONE1                     (resetdone1),
      .RXENELECIDLERESETB             (rxenelecidleresetb),
      .TXENPMAPHASEALIGN              (1'b0),
      .TXPMASETPHASE                  (1'b0),
      //-------------- Transmit Ports - 8b10b Encoder Control Ports --------------                                                                     
      .TXBYPASS8B10B0                 ({1'b0,1'b0}),
      .TXBYPASS8B10B1                 ({1'b0,1'b0}),
      .TXCHARDISPMODE0                ({1'b0,1'b0}),
      .TXCHARDISPMODE1                ({1'b0,1'b0}),
      .TXCHARDISPVAL0                 ({1'b0,1'b0}),
      .TXCHARDISPVAL1                 ({1'b0,1'b0}),
      .TXCHARISK0                     ({1'b0,tx_charisk_phy0}),
      .TXCHARISK1                     ({1'b0,tx_charisk_phy1}),
      .TXENC8B10BUSE0                 (1'b1),
      .TXENC8B10BUSE1                 (1'b1),
      .TXKERR0                        ({txkerr0_float_i,TXKERR0_OUT}),
      .TXKERR1                        ({txkerr1_float_i,TXKERR1_OUT}),
      .TXRUNDISP0                     ({txrundisp0_float_i,TXRUNDISP0_OUT}),
      .TXRUNDISP1                     ({txrundisp1_float_i,TXRUNDISP1_OUT}),
      //----------- Transmit Ports - TX Buffering and Phase Alignment ------------                                                                     
      .TXBUFSTATUS0                   (TXBUFSTATUS0),
      .TXBUFSTATUS1                   (),
      //---------------- Transmit Ports - TX Data Path interface -----------------                                                                     
      .TXDATA0                        (txdata_phy0),
      .TXDATA1                        (txdata_phy1),
      .TXDATAWIDTH0                   (1'b1),
      .TXDATAWIDTH1                   (1'b1),
      .TXOUTCLK0                      (),
      .TXOUTCLK1                      (),
      .TXRESET0                       (gtp_reset), //|phyreset0),                                                                                      
      .TXRESET1                       (gtp_reset), //|phyreset1),                                                                                      
      .TXUSRCLK0                      (gtp_txusrclk),
      .TXUSRCLK1                      (gtp_txusrclk),
      .TXUSRCLK20                     (gtp_txusrclk2),
      .TXUSRCLK21                     (gtp_txusrclk2),
      //------------- Transmit Ports - TX Driver and OOB signalling --------------                                                                     
      .TXBUFDIFFCTRL0                 (3'b001),
      .TXBUFDIFFCTRL1                 (3'b001),
      .TXDIFFCTRL0                    (3'b001),
      .TXDIFFCTRL1                    (3'b001),
      .TXINHIBIT0                     (1'b0),
      .TXINHIBIT1                     (1'b0),
      .TXN0                           (TXN0_OUT),
      .TXN1                           (TXN1_OUT),
      .TXP0                           (TXP0_OUT),
      .TXP1                           (TXP1_OUT),
      .TXPREEMPHASIS0                 (3'b000),
      .TXPREEMPHASIS1                 (3'b000),
      //------------------- Transmit Ports - TX PRBS Generator -------------------                                                                     
      .TXENPRBSTST0                   (1'b0),
      .TXENPRBSTST1                   (1'b0),
      //------------------ Transmit Ports - TX Polarity Control ------------------                                                                     
      .TXPOLARITY0                    (1'b0),
      .TXPOLARITY1                    (1'b0),
      //--------------- Transmit Ports - TX Ports for PCI Express ----------------                                                                     
      .TXDETECTRX0                    (1'b0),
      .TXDETECTRX1                    (1'b0),
      .TXELECIDLE0                    (txelecidle0),
      .TXELECIDLE1                    (txelecidle1),
      //------------------- Transmit Ports - TX Ports for SATA -------------------                                                                     
      .TXCOMSTART0                    (txcomstart0),
      .TXCOMSTART1                    (txcomstart1),
      .TXCOMTYPE0                     (txcomtype0), //this is 0 for cominit/comreset/  and 1 for comwake                                               
      .TXCOMTYPE1                     (txcomtype1)

      );

 

 

0 Kudos
3 Replies
Visitor ino1988
Visitor
10,509 Views
Registered: ‎09-10-2013

Re: virtex5 gtp for sata2

The simulation is ok.

 

Thanks

0 Kudos
Visitor ino1988
Visitor
10,497 Views
Registered: ‎09-10-2013

Re: virtex5 gtp for sata2

I have checked the 8b/10b code(010101 0101(b)) of 0x4A (d10.2) , the 8b/10b code(101010 1010(b)) of the data 0xB5(d21.5) is only one bit shifted. 

Can someone help me with this error.

 

Thanks a lot!!

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Moderator
Moderator
10,468 Views
Registered: ‎02-16-2010

Re: virtex5 gtp for sata2

are you finding this after OOB handshake is completed? have you sent comma characters before sending this data? Whether rxbyteisaligned is HIGH and rxbyterealgin does not pulse during this behavior?
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