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Observer patrickyip
Observer
9,266 Views
Registered: ‎08-06-2012

xapp1071 real-time test with serial ADC LVDS on Virtex6 V6 ML605

We tried to integrate the xapp1071 module in our FPGA system, as the LVDS interface with serial ADCs.

We found some problems in xapp1071 and need help!

 

We have demo board ML605 as reference design, and it is using one Virtex 6 (V6) with 4 x AD9276 running in 40 MSPS, 1-wire interface, 12bit data and MSB-first mode. The questions are listed below:

 

1)  We noticed that the xapp1071 / xapp866 is based on the TI ADS5273. The serial data output of this device is LSB-first mode (by default) and alighted with frame clock in LOW. However, we used the AD9276 (ADC from Analog Device) in our system which LVDS is MSB-first and alighted with frame clock in HIGH. So, I changed the “C_FrmPattern” to "000000111111" in “AdcFrame” module. Is it correct?

 

2) When the system is synchronized with the frame clock, the value of IntFrmDat should be “00,3F” ?

 

3) ADC in Test mode

We set the AD9276 to test mode and it kept sending “555” and “AAA” alternately. I can read out the data from the port “DatOut” in “AdcData” module ( using ChipScope ). However, the reading is something like:

 

DatOut:      … 555,xxx,AAA,yyy,555,xxx,AAA,yyy…        and I compared with the IntFrmDat,

IntFrmDat:  …3F, 00, 3F, 00, 3F, 00, 3F…

It seems that only when the IntFrmDat is “3F”, the value of DatOut is the correct value. Is it right?

 

4)  When I connected the AD9276 to a signal generator (sine wave, 2MHz, 0.5Vpp) and monitored the DatOut value. I noticed that the IntFrmDat does not stay in “00,3F”(fig1). I have pressed the reset button to reset this module and the IntFrmDat changed and stay in “07,30” (fig2). Pressed the reset button again and again, the IntFrmDat change to “34,0B” to “1E,21” to ….”00,3F”. Even though the IntFrmDat is back to”00,3F” (fig3) the DatOut is not the same as before (the source signal is not changed). Please see the attached jpg files for your reference. Is there any setup or step missing?

 

In the screen-capture jpg, the "dina0" is connected to “DatOut” port.

 

Thanks for help.

 

Patrick

 

-----

Fig 1. Correct data output pattern from AdcTopLevel.vhd (16-bit data from 12-bit ADC)
IntFrmDat = 00, 3F, 00, 3F, ...

 

-----

Fig 2. Wrong data output pattern from AdcTopLevel.vhd (IntFrmDat = 07, 30, 07, ...)
IntFrmDat = 07, 30, 07, 30, ...
We give reset to AdcTopLevel.vhd and sometimes it cannot give correct data pattern (fig 1 is very occasional correct patter after several resets to this module)

 

Fig 3. Wrong data output pattern from AdcTopLevel.vhd (IntFrmDat = 00, 3F, 00, 3F, ...)

IntFrmDat = 00, 3F, 00, 3F, ...
Thus IntFrmDat = 00, 3F, 00, 3F, ... cannot be regarded as the AdcTopLevel works correctly. What is wrong with AdcTopLevel.vhd
We give reset to AdcTopLevel.vhd and sometimes it cannot give correct data pattern (fig 1 is very occasional correct patter after several resets to this module)
But if we cannot use IntFrmDat output to learn whether AdcTopLevel.vhd is working properly. What can we do?

fig1_Frm_003F_sinewave.JPG
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7 Replies
Observer patrickyip
Observer
9,265 Views
Registered: ‎08-06-2012

Re: xapp1071 real-time test with serial ADC LVDS on Virtex6 V6 ML605

Fig 2. Wrong data output pattern from AdcTopLevel.vhd (IntFrmDat = 07, 30, 07, ...)
IntFrmDat = 07, 30, 07, 30, ...
We give reset to AdcTopLevel.vhd and sometimes it cannot give correct data pattern (fig 1 is very occasional correct patter after several resets to this module)

fig2_Frm_0730_sinewave.JPG
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Observer patrickyip
Observer
9,262 Views
Registered: ‎08-06-2012

Re: xapp1071 real-time test with serial ADC LVDS on Virtex6 V6 ML605

Fig 3. Wrong data output pattern from AdcTopLevel.vhd (16-bit data from 12-bit ADC)

IntFrmDat = 00, 3F, 00, 3F, ...
Thus IntFrmDat = 00, 3F, 00, 3F, ... cannot be regarded as the AdcTopLevel works correctly. What is wrong with AdcTopLevel.vhd
We give reset to AdcTopLevel.vhd and sometimes it cannot give correct data pattern (fig 1 is very occasional correct patter after several resets to this module)
But if we cannot use IntFrmDat output to learn whether AdcTopLevel.vhd is working properly. What can we do?

fig3_Frm_003F_sinewave_bad.JPG
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Observer patrickyip
Observer
9,227 Views
Registered: ‎08-06-2012

Re: xapp1071 real-time test with serial ADC LVDS on Virtex6 V6 ML605

Message from Tamagno (Much thanks!!! and that is very useful information)

-----

Hello Patrick,

This part of the project is stand by for now. I had other priorities. I will to go back soon but I did not use the design provided, I started one by my own and this give me a lot of problem. We are waiting some dedicate boards to start testing, I've just simulated on post-route netlist.

 

My configuration is very similar with yours: ML605, 4xAFE5808  running at 40 MSPS - 65 MSPS, 1-wire interface, 12bit data and MSB-first mode.

There are a lot of information that is not detailed at xapp1071 or xapp866, for example double nibble problem. I found more details at xapp524, is very similar with xapp1071 and

xapp866 but for 7 series FPGAs.

 

About your questions, I didn´t work with xapp1071 design but i saw something that maybe can help.

 

1) We noticed that the xapp1071 / xapp866 is based on the TI ADS5273. The serial data output of this device is LSB-first mode (by default) and alighted with frame clock in LOW. However, we used the AD9276 (ADC from Analog Device) in our system which LVDS is MSB-first and alighted with frame clock in HIGH. So, I changed the “C_FrmPattern” to "000000111111" in “AdcFrame” module. Is it correct?

A: Like I said I didn´t work with xapp1071 but looking for more information I downloaded the xapp524 design and at: xapp524\LvdsSerialAdc\Projects\Adc_Interface\Libraries\AdcFrame_Lib\Documents there is a pdf presentation called "Visio-AdcFrame.pdf". This presentation shows some detail about frame alignment.

I don´t know if you just changed the alignment from "111111000000" to "000000111111" but you need take care with one thing. In aligment, you don´t know what border from ISERDESE collect first. So, in case of  "111111000000" pattern, you can use a pattern like "011111100000" and a bit-swap version "101111010000" to detect the border. Take a look at page 6 of this presentation, this might help.

 

2) When the system is synchronized with the frame clock, the value of IntFrmDat should be “00,3F” ?

 

A: I believed that in your case, using a 12 bits frame pattern "000000111111", 00,3F = 00000000_00111111 can be correct. This 2 bits can be just blank bits added to complete 16 bits at frame output.

 

3) ADC in Test mode

We set the AD9276 to test mode and it kept sending “555” and “AAA” alternately. I can read out the data from the port “DatOut” in “AdcData” module ( using ChipScope ). However, the reading is something like:

 

DatOut:      … 555,xxx,AAA,yyy,555,xxx,AAA,yyy…        and I compared with the IntFrmDat,

IntFrmDat:  …3F, 00, 3F, 00, 3F, 00, 3F…

It seems that only when the IntFrmDat is “3F”, the value of DatOut is the correct value. Is it right?

 

A:When you say: " it kept sending “555” and “AAA” alternately" you mean 555 in one frame period and AAA in the next frame period? If yes, looks like it is working, but the data is valid just at half period. If possible try to configure your AD to send incremental data, you can check swap problems..

 

4)  When I connected the AD9276 to a signal generator (sine wave, 2MHz, 0.5Vpp) and monitored the DatOut value. I noticed that the IntFrmDat does not stay in “00,3F”(fig1). I have pressed the reset button to reset this module and the IntFrmDat changed and stay in “07,30” (fig2). Pressed the reset button again and again, the IntFrmDat change to “34,0B” to “1E,21” to ….”00,3F”. Even though the IntFrmDat is back to”00,3F” (fig3) the DatOut is not the same as before (the source signal is not changed). Please see the attached jpg files for your reference. Is there any setup or step missing?

A: Sorry, but I really don´t know what is happening.

 

Iliézer Tamagno

 

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Newbie anupr
Newbie
8,987 Views
Registered: ‎05-01-2013

Re: xapp1071 real-time test with serial ADC LVDS on Virtex6 V6 ML605

hello Patrick, I am seeing very similar problems with a 4dsp card I am using to get ADC samples into my FPGA design. Can you please share your experience on what you did to fix your problem? I am referring to the clipping of the signals as shown in your waveform screenshot.

Thanks

Anup

 

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Visitor ivanov_marko
Visitor
8,492 Views
Registered: ‎11-11-2013

Re: xapp1071 real-time test with serial ADC LVDS on Virtex6 V6 ML605

Hi,

I am using the xapp1071 with ADS5282. 12 bit, LSB, 65 MSPS.

 

But the reference design has problems with:

in AdcFrame.vhd there is

 

signal IntFrmSrdsDatEvn             : std_logic_vector( (FrmBits(C_AdcBits)/3) - 1 downto 0);

 AND

DataIn  => IntFrmSrdsDatEvn, -- in [3:0]

 

IntFrmSrdsDatEvn turns out to be 3 bit vector and DataIn is by default 4!

 

How do you manage that?

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Visitor ivanov_marko
Visitor
8,426 Views
Registered: ‎11-11-2013

Re: xapp1071 real-time test with serial ADC LVDS on Virtex6 V6 ML605

Hi everybody! This XAPP is very useful in terms of understanding but acctualy, it is much easier to build something much more simple like described in http://e2e.ti.com/support/data_converters/high_speed_data_converters/f/68/t/47555.aspx by Richard.

Follow these instructions and you will be done very fast.

Best regards

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Explorer
Explorer
6,986 Views
Registered: ‎02-05-2008

Re: xapp1071 real-time test with serial ADC LVDS on Virtex6 V6 ML605

Hi I am getting similar issue. Did you solve this? Can you update? Jothi
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