10-30-2012 03:34 AM
1) Implementation: It was said in app note xapp1071, that it has been tested on "ML605 demonstration board with FMC_101 loopback interface" (xapp1071, page 26). Where can i find how to set up the test? Is it referrring to FMC XM101 board from Xilinx?
I find that i cannot run the simulations in ModelSim v6.5d. After some modifications, it can run. However, the output file by AdcToplevel_Checker.vhd inside AdcInVec.txt seems to be always empty.
3) ISE compile errors: I have tried to compile the source code given by xapp1071, but there are errors
ERROR:PhysDesignRules:368 - The signal <AdcIntrfcStats_pin<4>_OBUF>
is incomplete. The signal is not driven by any source pin in the design.
ERROR:PhysDesignRules:10 - The network <AdcIntrfcStats_pin<4>_OBUF>
is completely unrouted.
Just compile the ise-logic project file inside xapp1071.zip
10-30-2012 06:44 AM
It's not uncommon to have errors when you build an app-note design in a different version
of ISE from the one originally used. Xapp 1071 is dated June of 2010. The errors you posted
may have only been warnings in a prior ISE release.
From the XAPP table 2:
Synthesis tool / version XST version in ISE® software v11.4
Implementation tool / version ISE software v11.4
You may have better luck using the same version (or 11.5)
10-30-2012 07:22 PM
10-30-2012 08:14 PM
10-30-2012 08:15 PM
10-31-2012 09:32 PM
11-08-2012 12:12 AM
Below is a summary of my questions:
Q1) There are some errors with ISE v13.2 during implementation? (Translate, Place-&-Route in ISE) How to solve the errors? Xilinx gave me the latest version “Ml605_Gen_Xapp1071_Hdl_10Nov11” (2011-Nov-10), after deactivated the DRC option of Bitgen, it passes. Why? Can such errors be ignored?
Can anyone successfully run simulations? It cannot work in xapp1071. AdcInVec.txt output is of only the header. The file is of empty outputs (no vectors recorded).
I find that xapp866 is very similar to xapp1071 (by the same author), but xapp866 for Virtex 5, xapp1071 for Virtex 6.
The file "AdcIntInVec.txt" (xapp866) can show the output vectors (not empty), written by AdcToplevel_Checker.vhd
This file is similar to AdcInVec.txt in xapp1071.
Q3) Test set-up on ML605:
How to test the codes in ML605?
Is there any document or block diagram of connections of test set up with ML605? Where can i find such information?
Is it just using FMC XM101 board as a loop-back test? How is it connected? Where is the test program for the micro-processor? Any test procedures? i cannot find it in the zip files.
I have a small board FMC XM104. If it is just loop-back of outputs & inputs, can this board be used for the test too?
11-14-2012 09:17 AM
Answers to your questions:
1: The XM101 board is a cable loopback FMC board from Xilinx. I suppose you can obtain it via your local Xilinx channels.
2: As written in the readme.txt file, simulations of the design are not done in Modelsim but with ISIM, the Xilinx ISE simulator tool. That is probably why things go different with Modelsim.
3: ISE implementation errors.
Strange because the design has been checked by several people in Xilinx.
This will be handled via your FAE.
11-15-2012 08:15 AM
> 1: The XM101 board is a cable loopback FMC board from Xilinx. I suppose you can obtain it via your local Xilinx channels.
This module was released to production see: http://www.xilinx.com/products/boards-and-kits/HW-FMC-XM101-G.htm
08-16-2013 05:26 AM
I encountered a problem when I applied Xapp524 to my design. The output of my ADC is 8 channels 16 bits output with DCLK and FCLK. And it use 1 pair LVDS wire for every channel.
But when I read the reference design Xapp524, in the file of "AdcClock.vhd", BUFR_DIVIDE=4 for a BUF.Is it means that
the design Xapp524 is only fit for ADC in 2 pair LVDS wires mode? And that, can my design with ADC in 1 pair wire mode change BUFR_DIVIDE=8 ?