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Posts: 1
Registered: ‎04-20-2008

CRC (Cyclic REdundancy Check) for Verilog

i am brand new to Verilog, and have to make a serial and parallel CRC for my design class.

i am a little confused on how the CRC works though.   on wikipedia: http://en.wikipedia.org/wiki/Computation_of_CRC
the .gifs show the data being streamed in, then CRC'd with a full word of 0s.   Is this always the process? Are there always a full string of zeroes following the initial message, or was that an arbitrary case shown for demonstration purposes in that .gif?

thank you fellow engineersPreview Post
Posts: 369
Registered: ‎12-03-2007

Re: CRC (Cyclic REdundancy Check) for Verilog

I've built a website - http://OutputLogic.com -  with online tool that generates a Verilog code for parallel CRC given data width and polynomial coefficients.

There is also a short post that describes a parallel CRC generation algorithm for Verilog.


Hope that helps



Posts: 1
Registered: ‎02-17-2012

Re: CRC (Cyclic REdundancy Check) for Verilog

nice one 

Posts: 1
Registered: ‎02-13-2016

Re: CRC (Cyclic REdundancy Check) for Verilog

Sir I have went through your website http://outputlogic.com/

and i ve written test bench code for CRC32 802.3 with 32 bit polynomial width  but i didnt get waveform

please help me regarding following test bench code


module tb_v;

// Inputs
reg [31:0] data_in;
reg crc_en;
reg rst;
reg clk;

// Outputs
wire [31:0] crc_out;

// Instantiate the Unit Under Test (UUT)
crc uut (

initial begin
// Initialize Inputs
#1 clk = 0;
#1 crc_en = 0;
#1 rst=0;
data_in =32'h0000000000000000;
forever begin
data_in =32'h01234567891234567;
#1 clk = ~clk;
#1 rst = ~rst;
#1 crc_en = ~crc_en;


// Wait 100 ns for global reset to finish
#1000 $stop;

// Add stimulus here

$monitor("At time %2t, crc_en = %d, rst = %d, data_in = %d, crc_out = %d",
$time, crc_en, rst, data_in, crc_out);



CRC (Cyclic REdundancy Check) for Verilog