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Visitor yasamin
Visitor
2,374 Views
Registered: ‎10-11-2008

DDR2_simulation

I used MIG1.7 to generate controller for DDR2_SDRAM. I used the controller with DCM and Testbench . I want to simulate it by modelsim.

But the "init_done" signal  do not assert(always is low).

It is notice that i simulate a DDR before and i do not have any problem.

please help me .

 

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