09-09-2014 06:38 AM
I am using SERDES to transmit data from one Virtex 7 to another Virtex 7 via a VPX plus connector (wafer cable connected between two VPX backplanes). The SERDES modules use LVDS at 1.8V. I have slowed the clock down to 156.25MHz for the serial clock and 39.063MHz for the divide-by clock in DDR mode.
I have tested that the FPGA to FPGA connections are good. And, in simulation, my SERDES Tx to SERDES Rx works as designed (there is a bitslip phase, followed by normal data transmission). However, when using chipscope to look at the Parallel data from the SERDES Rx in practice, I get all 1's, though I am chaning the Tx data. I'm stumped on how to proceed. I'm not able to see if the transmitted data is valid since any attempt to register and chipscope the serial Tx Data fails during Place & Route. I can verify that I am sending Valid parallel data to the SERDES - but that seems to be the extent of my validation. I am asserting both a clock and io reset (the IO reset being deasserted last) and do have Bitslip logic inserted.
Any advice on how to debug would be greatly appreciated.
Here are some parameters for the SERDES:
Differential, Serialization factor: 8, Data width 12, differential clock forwarding from Tx to Rx Module, no delay for the Rx module currently.
09-09-2014 07:03 AM
Did you run behavioral simulation or post route simulation? you need to verify your design using post route simulation for ideal results.
Is your design timing closed? In case the timing is not closed, the design may not work on hardware. Kindly write all the basic timing constraints and check.
Check the clock signal integrity. Since it is not a very speed clock, i dont expect many problems.
Try using the SelectiO wizard generated core with the settings which you gave and check the example design on HW.
Since you are using I expect you have a training pattern? Is this correct? In case you dont have it, it is better to have one.
09-09-2014 08:23 AM
Thanks. Those are good suggestions. I will instantiate the example design and check my constraints.
Regarding the simulation, I ran the behavioral simulation only since I actually only pulled out the SERDES portions of both designs and modeled the rest. I'm not sure if it's possible to obtain post-route timing for a module as opposed to the top level netlist. Simulating both FPGAs would not be very feasible. I'll look into this.
I am using a training pattern. I haven't checked the signal integrity of the clock. That should be possible on the system - as is checking the data signals from the Tx module.
Thanks again - I will update as I can.
09-09-2014 10:26 AM
Thanks for the update. In case it should take sometime to try these options, i would recommend to close this tread and refer this once you have tried these options.
04-13-2018 02:37 AM
Were you able to resolve this issue? I am facing same issue now, I am using an ISERDES, output is always '0',
It works in behavioral simulation.
Would appreciate any help.